AMD AMD-K6-2/500AFX Data Sheet - Page 262
Single Step Trap, Task Switch Trap
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Interrupt 01h. The following events are considered debug traps that cause the processor to generate an Interrupt 01h exception: s Enabled breakpoints for data and I/O cycles s Single Step Trap s Task Switch Trap The following events are considered debug faults that cause the processor to generate an Interrupt 01h exception: s Enabled breakpoints for instruction execution s BD bit in DR6 set to 1 Interrupt 03h. The INT 3 instruction is defined in the x86 architecture as a breakpoint instruction. This instruction causes the processor to generate an Interrupt 03h exception. This exception is a debug trap because the debugger is called following the execution of the INT 3 instruction. The INT 3 instruction is a one-byte instruction (opcode CCh) typically used to insert a breakpoint in software by writing CCh to the address of the first byte of the instruction to be trapped (the target instruction). Following the trap, if the target instruction is to be executed, the debugger must replace the INT 3 instruction with the first byte of the target instruction. 242 Test and Debug Chapter 11