AMD AMD-K6-2/500AFX Data Sheet - Page 219
Writethrough versus Writeback Coherency States, 7.12 A20M# Masking of Cache Accesses
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 7.11 7.12 Chapter 7 Writethrough versus Writeback Coherency States The terms writethrough and writeback apply to two related concepts in a read-write cache like the AMD-K6-2 processor L1 data cache. The following conditions apply to both the writethrough and writeback modes: s Memory Writes-A relationship exists between external memory writes and their concurrence with cache updates: • An external memory write that occurs concurrently with a cache update to the same location is a writethrough. Writethroughs are driven as single cycles on the bus. • An external memory write that occurs after the processor has modified a cache line is a writeback. Writebacks are driven as burst cycles on the bus. s Coherency State-A relationship exists between MESI coherency states and writethrough-writeback coherency states of lines in the cache as follows: • Shared and invalid MESI lines are in the writethrough state. • Modified and exclusive MESI lines are in the writeback state. A20M# Masking of Cache Accesses Although the processor samples A20M# as a level-sensitive input on every clock edge, it should only be asserted in Real mode. The processor applies the A20M# masking to its tags, through which all programs access the caches. Therefore, assertion of A20M# affects all addresses (cache and external memory), including the following: s Cache-line fills (caused by read misses or write allocates) s Cache writethroughs (caused by write misses or write hits to lines in the shared state) However, A20M# does not mask writebacks or invalidations caused by the following actions: s Internal snoops s Inquire cycles s The FLUSH# signal s Writing to the PFIR (AMD-K6-2/[F:8] only) s The WBINVD instruction Cache Organization 199