AMD AMD-K6-2/500AFX Data Sheet - Page 73
Processor State Observability Register (PSOR), Flush/Invalidate Register (PFIR)
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Processor State Observability Register (PSOR) The AMD-K6-2 processor Model 8/[F:8] provides the Processor State Observability Register (PSOR) (see Figure 50). 63 9 87 432 0 N O L STEP BF 2 Reserved Symbol Description Bit NOL2 No L2 Functionality 8 STEP Processor Stepping 7-4 BF Bus Frequency Divisor 2-0 Figure 50. Processor State Observability Register (PSOR) Page Flush/Invalidate Register (PFIR) The AMD-K6-2 processor Model 8/[F:8] contains the Page Flush/Invalidate Register (PFIR) (see Figure 51) that allows cache invalidation and optional flushing of a specific 4-Kbyte page from the linear address space. For more detailed information on PFIR, see "PFIR" on page 195. 63 32 31 12 11 9 8 7 10 LINPAGE P F F / I Symbol LINPAGE PF F/I Reserved Description 20-bit Linear Page Address Page Fault Occurred Flush/Invalidate Command Bit 31-12 8 0 Figure 51. Page Flush/Invalidate Register (PFIR) Chapter 3 Software Environment 53