AMD AMD-K6-2/500AFX Data Sheet - Page 147

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 5 Bus Cycles The following sections describe and illustrate the timing and relationship of bus signals during various types of bus cycles. A representative set of bus cycles is illustrated. 5.1 Timing Diagrams The timing diagrams illustrate the signals on the external local bus as a function of time, as measured by the bus clock (CLK). Throughout this chapter, the term clock refers to a single bus-clock cycle. A clock extends from one rising CLK edge to the next rising CLK edge. The processor samples and drives most signals relative to the rising edge of CLK. The exceptions to this rule include the following: s BF[2:0]-Sampled on the falling edge of RESET s FLUSH#, BRDYC#-Sampled on the falling edge of RESET, also sampled on the rising edge of CLK s All inputs and outputs are sampled relative to TCK in Boundary-Scan Test Mode. Inputs are sampled on the rising edge of TCK, outputs are driven off of the falling edge of TCK. For each signal in the timing diagrams, the High level represents 1, the Low level represents 0, and the Middle level represents the floating (high-impedance) state. When both the High and Low levels are shown, the meaning depends on the signal. A single signal indicates 'don't care'. In the case of bus activity, if both High and Low levels are shown, it indicates the processor, alternate master, or system logic is driving a value, but this value may or may not be valid. (For example, the value on the address bus is valid only during the assertion of ADS#, but addresses are also driven on the bus at other times.) Figure 53 defines the different waveform representations. Chapter 5 Bus Cycles 127