AMD AMD-K6-2/500AFX Data Sheet - Page 207

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Write to a Sector Write Allocate Limit 63 When the processor performs a cache line fill from a different page than the address saved in the CCR, the CCR is updated with the new page address. If the address of a pending write cycle matches the tag address of a valid cache sector, but the addressed cache line within the sector is marked invalid (a sector hit but a cache line miss), then the processor performs a write allocate. The pending write cycle is determined to be cacheable because the sector hit indicates the presence of at least one valid cache line in the sector. The two cache lines within a sector are guaranteed by design to be within the same page. The AMD-K6-2 processor uses two mechanisms that are programmable within the Write Handling Control Register (WHCR) to enable write allocations for write cycles that address a definable area, or a special 1-Mbyte memory area. The format of the WHCR differs between the AMD-K6-2 processor Model 8/[7:0] and the AMD-K6-2 processor Model 8/[F:8]. WHCR - Model 8/[7:0]. This WHCR contains three fields - the WCDE bit, the Write Allocate Enable Limit (WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit (See Figure 79 on page 187). For proper functionality, always program the WCDE bit to 0. 987 0 WAELIM 10 W A E 1 5 M Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program to 0 8 Write Allocate Enable Limit 7-1 Write Allocate Enable 15-to-16-Mbyte 0 Note: Hardware RESET initializes this MSR to all zeros. Figure 79. Write Handling Control Register (WHCR) - Model 8/[7:0] Write Allocate Enable Limit - Model 8/[7:0]. The WAELIM field is 7 bits wide. This field, multiplied by 4 Mbytes, defines an upper memory limit. Any pending write cycle that addresses memory below this limit causes the processor to perform a write allocate Chapter 7 Cache Organization 187