AMD AMD-K6-2/500AFX Data Sheet - Page 60

AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition Bit Description R/W 63-48 SYSRET CS and SS Selector Base R/W 47-32 SYSCALL CS and SS Selector Base R/W 31-0 Target EIP Address R/W Write Handling Control Register (WHCR)-Model 8/[7:0]. The write handling control register (WHCR) is a MSR that contains three fields - the WCDE bit, write allocate enable limit (WAELIM) field, and the write allocate enable 15-to-16-Mbyte (WAE15M) bit. Figure 36 shows the format of WHCR. See "Write Allocate" on page 186 for more information. Note: The WHCR register as defined in the Model 8/[7:0] has changed in the Model 8/[F:8]. See "Write Handling Control Register (WHCR)-Model 8/[F:8]" on page 51. 63 9 87 10 W A 0 WAELIM E 1 5 M Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program to 0 8 Write Allocate Enable Limit 7-1 Write Allocate Enable 15-to-16-Mbyte 0 Note: Hardware RESET initializes this MSR to all zeros. Figure 36. Write Handling Control Register (WHCR)-Model 8/[7:0] Memory Management Registers The AMD -K 6-2 processor controls segm ented m emory management with the registers listed in Table 8. Figure 37 on page 41 shows the formats of these registers. Table 8. Memory Management Registers Register Name Global Descriptor Table Register Interrupt Descriptor Table Register Local Descriptor Table Register Task Register Function Contains a pointer to the base of the global descriptor table Contains a pointer to the base of the interrupt descriptor table Contains a pointer to the local descriptor table of the current task Contains a pointer to the task state segment of the current task 40 Software Environment Chapter 3