AMD AMD-K6-2/500AFX Data Sheet - Page 101
DNow!™ Instructions, Table 16., MMX™ Instructions continued, Instruction Mnemonic, Prefix, Bytes
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Table 16. MMX™ Instructions (continued) Instruction Mnemonic Prefix First ModR/M Decode RISC86 Byte(s) Byte Byte Type Operations Note PUNPCKHDQ mmreg1, mmreg2 0Fh 6Ah 11-xxx-xxx short meu PUNPCKHDQ mmreg, mem64 0Fh 6Ah mm-xxx-xxx short mload, meu PUNPCKHWD mmreg1, mmreg2 0Fh 69h 11-xxx-xxx short meu PUNPCKHWD mmreg, mem64 0Fh 69h mm-xxx-xxx short mload, meu PUNPCKLBW mmreg1, mmreg2 0Fh 60h 11-xxx-xxx short meu PUNPCKLBW mmreg, mem32 0Fh 60h mm-xxx-xxx short mload, meu PUNPCKLDQ mmreg1, mmreg2 0Fh 62h 11-xxx-xxx short meu PUNPCKLDQ mmreg, mem32 0Fh 62h mm-xxx-xxx short mload, meu PUNPCKLWD mmreg1, mmreg2 0Fh 61h 11-xxx-xxx short meu PUNPCKLWD mmreg, mem32 0Fh 61h mm-xxx-xxx short mload, meu PXOR mmreg1, mmreg2 0Fh EFh 11-xxx-xxx short meu PXOR mmreg, mem64 0Fh EFh mm-xxx-xxx short mload, meu Note: ** Bits 2, 1, and 0 of the modR/M byte select the integer register. Table 17. 3DNow!™ Instructions Instruction Mnemonic Prefix Opcode ModR/M Decode Byte(s) Byte Byte Type RISC86 Operations Note FEMMS 0Fh 0Eh vector PAVGUSB mmreg1, mmreg2 0Fh, 0Fh BFh 11-xxx-xxx short meu PAVGUSB mmreg, mem64 0Fh, 0Fh BFh mm-xxx-xxx short mload, meu PF2ID mmreg1, mmreg2 0Fh, 0Fh 1Dh 11-xxx-xxx short meu PF2ID mmreg, mem64 0Fh, 0Fh 1Dh mm-xxx-xxx short mload, meu PFACC mmreg1, mmreg2 0Fh, 0Fh AEh 11-xxx-xxx short meu PFACC mmreg, mem64 0Fh, 0Fh AEh mm-xxx-xxx short mload, meu PFADD mmreg1, mmreg2 0Fh, 0Fh 9Eh 11-xxx-xxx short meu PFADD mmreg, mem64 0Fh, 0Fh 9Eh mm-xxx-xxx short mload, meu PFCMPEQ mmreg1, mmreg2 0Fh, 0Fh B0h 11-xxx-xxx short meu PFCMPEQ mmreg, mem64 0Fh, 0Fh B0h mm-xxx-xxx short mload, meu PFCMPGE mmreg1, mmreg2 0Fh, 0Fh 90h 11-xxx-xxx short meu Notes: 1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched. 2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2 processor, this instruction performs in the same manner as the PREFETCH instruction. Chapter 3 Software Environment 81