AMD AMD-K6-2/500AFX Data Sheet - Page 223
Memory Type Range Registers, UC/WC Cacheability Control Register (UWCCR), UC/WC Cacheability
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 8.2 Memory Type Range Registers UC/WC Cacheability Control Register (UWCCR) The AMD-K6-2 processor Model 8/[F:8] provides two variablerange Memory Type Range Registers (MTRRs)-MTRR0 and MTRR1-that each specify a range of memory. Each range can be defined as one of the following memory types: s Uncacheable (UC) memory-Memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. Memory write cycles are targeted at the specified memory address and a write allocation does not occur. s Write-Combining (WC) memory-Memory read cycles are sourced directly from the specified memory address and the processor does not allocate a cache line. The processor conditionally combines data from multiple noncacheable write cycles that are addressed within this range into a merge buffer. Merging multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls, thereby increasing the overall system performance. This memory type is applicable for linear video frame buffers. The MTRRs are accessed by addressing the 64-bit MSR known as the UC/WC Cacheability Control Register (UWCCR). The MSR address of the UWCCR is C000_0085h. Following reset, all bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits of the UWCCR register) defines the size and memory type of range 0 and MTRR1 (upper 32 bits) defines the size and memory type of range 1 (see Figure 83). Chapter 8 Write Merge Buffer 203