AMD AMD-K6-2/500AFX Data Sheet - Page 212
Prefetching, Hardware Prefetching, 7.9 Cache States, Hardware
View all AMD AMD-K6-2/500AFX manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 212 highlights
AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 7.8 Prefetching Hardware Prefetching The AMD-K6-2 processor conditionally performs cache prefetching which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. From the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. The burst read cycles do not occur back-to-back (wait states occur) if the processor is not ready to start a new cycle, if higher priority data read or write requests exist, or if NA# (next address) was sampled negated. Wait states can also exist between burst cycles if the processor samples AHOLD or BOFF# asserted. Software Prefetching The 3DNow! technology includes an instruction called PREFETCH that allows a cache line to be prefetched into the data cache. Unlike prefetching under hardware control, software prefetching only fetches the cache line specified by the operand of the PREFETCH instruction, and does not attempt to fetch the other cache line in the sector. The PREFETCH instruction format is defined in Table 17, "3DNow!™ Instructions," on page 81. For more detailed information, see the 3DNow!™ Technology Manual, order# 21928. 7.9 Cache States Table 36 shows all the possible cache-line states before and after program-generated accesses to individual cache lines. The table includes the correspondence between MESI states and writethrough or writeback states for lines in the data cache. 192 Cache Organization Chapter 7