AMD AMD-K6-2/500AFX Data Sheet - Page 154

AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Misaligned Single-Transfer Memory Read and Write Figure 56 shows a misaligned (split) memory read followed by a misaligned memory write. Any cycle that is not aligned as defined in "SCYC (Split Cycle)" on page 117 is considered misaligned. When the processor encounters a misaligned access, it determines the appropriate pair of bus cycles-each with its own ADS# and BRDY# - required to complete the access. The AMD-K6-2 processor performs misaligned memory reads and memory writes using least-significant bytes (LSBs) first followed by most-significant bytes (MSBs). Table 26 shows the order. In the first memory read cycle in Figure 56, the processor reads the least-significant bytes. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to read the most-significant bytes to complete the misaligned transfer. Table 26. Bus-Cycle Order During Misaligned Transfers Type of Access Memory Read Memory Write First Cycle LSBs LSBs Second Cycle MSBs MSBs Similarly, the misaligned memory write cycle in Figure 56 on page 135 transfers the LSBs to the memory bus first. In the next cycle, after the processor samples BRDY# asserted, the MSBs are written to the memory bus. 134 Bus Cycles Chapter 5