AMD AMD-K6-2/500AFX Data Sheet - Page 75
Table 14., Integer Instructions, register or memory form. If modR/M bits 7 and 6 are documented
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet The second and third columns list all applicable opcode bytes. The fourth column lists the modR/M byte when used by the instruction. The modR/M byte defines the instruction as a register or memory form. If modR/M bits 7 and 6 are documented as mm (memory form), mm can only be 10b, 01b or 00b. The fifth column lists the type of instruction decode - short, long, and vector. The AMD-K6-2 processor decode logic can process two short, one long, or one vector decode per clock. The sixth column lists the type of RISC86 operation(s) required for the instruction. The operation types and corresponding execution units are as follows: s load, fload, mload-load unit s store, fstore, mstore-store unit s alu-either of the integer execution units s alux-integer X execution unit only s branch-branch condition unit s float-floating-point execution unit s meu-Multimedia execution units for MMX and 3DNow! instructions s limm-load immediate, instruction control unit Table 14. Integer Instructions Instruction Mnemonic AAA AAD AAM AAS ADC mreg8, reg8 ADC mem8, reg8 ADC mreg16/32, reg16/32 ADC mem16/32, reg16/32 ADC reg8, mreg8 ADC reg8, mem8 ADC reg16/32, mreg16/32 ADC reg16/32, mem16/32 ADC AL, imm8 First Second Byte Byte ModR/M Decode Byte Type 37h vector D5h 0Ah vector D4h 0Ah vector 3Fh vector 10h 11-xxx-xxx vector 10h mm-xxx-xxx vector 11h 11-xxx-xxx vector 11h mm-xxx-xxx vector 12h 11-xxx-xxx vector 12h mm-xxx-xxx vector 13h 11-xxx-xxx vector 13h mm-xxx-xxx vector 14h vector RISC86 Operations Chapter 3 Software Environment 55