AMD AMD-K6-2/500AFX Data Sheet - Page 139

21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet 4.45 Summary Sampled STPCLK# (Stop Clock) Input, Internal Pullup The assertion of STPCLK# causes the processor to enter the Stop Grant state, during which the processor's internal clock is stopped. From the Stop Grant state, the processor can subsequently transition to the Stop Clock state, in which the bus clock CLK is stopped. Upon recognizing STPCLK#, the processor performs the following actions, in the order shown: 1. Flushes its instruction pipelines 2. Completes all pending and in-progress bus cycles 3. Acknowledges the STPCLK# assertion by executing a Stop Grant special bus cycle (see Table 25 on page 126) 4. Stops its internal clock after BRDY# of the Stop Grant special bus cycle is sampled asserted and after EWBE# is sampled asserted (if EWBE# is masked off, then entry into the Stop Grant state is not affected by EWBE#) 5. Enters the Stop Clock state if the system logic stops the bus clock CLK (optional) See "Clock Control" on page 243 for more details regarding clock control. STPCLK# is sampled as a level-sensitive input on every clock edge but is not recognized until the next instruction boundary. System logic can drive the signal either synchronously or asynchronously. If it is asserted asynchronously, it must be asserted for a minimum pulse width of two clocks. STPCLK# must remain asserted until recognized, which is indicated by the completion of the Stop Grant special cycle. 4.46 Summary TCK (Test Clock) Input, Internal Pullup TCK is the clock for boundary-scan testing using the Test Access Port (TAP). See "Boundary-Scan Test Access Port (TAP)" on page 223 for details regarding the operation of the TAP controller. Chapter 4 Signal Descriptions 119