AMD AMD-K6-2/500AFX Data Sheet - Page 238
I/O Trap Dword, Bit 0
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 10.7 218 Upon entry into SMM, the halt restart slot is defined as follows: s Bits 15-1-Reserved s Bit 0-Point of entry to SMM: 1 = entered from Halt state 0 = not entered from Halt state After entry into the SMI handler and before returning from SMM, the halt restart slot can be written using the following definition: s Bits 15-1-Reserved s Bit 0-Point of return when exiting from SMM: 1 = return to Halt state 0 = return to next instruction after the HLT instruction If the return from SMM takes the processor back to the Halt state, the HLT instruction is not re-executed, but the Halt special bus cycle is driven on the bus after the return. I/O Trap Dword If the assertion of SMI# is recognized during the execution of an I/O instruction, the I/O trap dword at offset FFA4h in the SMM state-save area contains information about the instruction. The fields of the I/O trap dword are configured as follows: s Bits 31-16-I/O port address s Bits 15-4-Reserved s Bit 3-REP (repeat) string operation (1 = REP string, 0 = not a REP string) s Bit 2-I/O string operation (1 = I/O string, 0 = not an I/O string) s Bit 1-Valid I/O instruction (1 = valid, 0 = invalid) s Bit 0-Input or output instruction (1 = INx, 0 = OUTx) Table 45 shows the format of the I/O trap dword. Table 45. I/O Trap Dword Configuration 31-16 I/O Port Address 15-4 Reserved 3 REP String Operation 2 I/O String Operation 1 Valid I/O Instruction 0 Input or Output System Management Mode (SMM) Chapter 10