AMD AMD-K6-2/500AFX Data Sheet - Page 15
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Execution Latency and Throughput of Execution Units . . . . . 16 General-Purpose Registers 22 General-Purpose Register Doubleword, Word, and Byte Names 23 Segment Registers 24 AMD-K6®-2 Processor Model 8/[7:0] MSRs 37 Extended Feature Enable Register (EFER) - Model 8[7:0]Definition 39 SYSCALL/SYSRET Target Address Register (STAR) Definition 40 Memory Management Registers 40 Application Segment Types 47 System Segment and Gate Types 48 Summary of Exceptions and Interrupts 49 AMD-K6®-2 Processor Model 8/[F:8] MSRs 50 Extended Feature Enable Register (EFER)- Model 8/[F:8] Definition 51 Integer Instructions 55 Floating-Point Instructions 74 MMX™ Instructions 78 3DNow!™ Instructions 81 Processor-to-Bus Clock Ratios 92 Output Pin Float Conditions 122 Input Pin Types 124 Output Pin Float Conditions 125 Input/Output Pin Float Conditions 125 Test Pins 125 Bus Cycle Definition 126 Special Cycles 126 Bus-Cycle Order During Misaligned Transfers 134 A[4:3] Address-Generation Sequence During Bursts 136 Bus-Cycle Order During Misaligned I/O Transfers 141 Interrupt Acknowledge Operation Definition 162 Encodings For Special Bus Cycles 164 Output Signal State After RESET 174 Register State After RESET 175 PWT Signal Generation 182 PCD Signal Generation 182 CACHE# Signal Generation 183 Data Cache States for Read and Write Accesses 193 Cache States for Inquire Cycles, Snoops, Flushes, and Invalidation 197 List of Tables xv