AMD AMD-K6-2/500AFX Data Sheet - Page 58
Time Stamp Counter TSC, Machine-Check Type Register MCTR
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 63 54 0 MCTR Reserved Figure 31. Machine-Check Type Register (MCTR) Test Register 12 (TR12). Test register 12 provides a method for disabling the L1 caches. Figure 32 shows the format of TR12. 63 43 2 1 0 C I Reserved Symbol Description Bit CI Cache Inhibit Bit 3 Figure 32. Test Register 12 (TR12) Time Stamp Counter. Wi t h e a ch p ro c e s s o r c l o ck cy c l e , t h e processor increments the 64-bit time stamp counter (TSC) MSR. Figure 33 shows the format of the TSC. 63 0 TSC Figure 33. Time Stamp Counter (TSC) 38 Software Environment Chapter 3
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38
Software Environment
Chapter 3
AMD-K6
®
-2 Processor Data Sheet
21850J/0—February 2000
Preliminary Information
Figure 31.
Machine-Check Type Register (MCTR)
Test Register 12 (TR12).
Test register 12 provides a method for
disabling the L1 caches. Figure 32 shows the format of TR12.
Figure 32.
Test Register 12 (TR12)
Time Stamp Counter.
With each processor clock cycle, the
processor increments the 64-bit time stamp counter (TSC) MSR.
Figure 33 shows the format of the TSC.
Figure 33.
Time Stamp Counter (TSC)
5
4
0
63
MCTR
Reserved
4
2
1
0
63
C
I
3
Reserved
Symbol
Description
Bit
CI
Cache Inhibit Bit
3
0
63
TSC