AMD AMD-K6-2/500AFX Data Sheet - Page 156
Burst Reads and Pipelined Burst Reads, Table 27., A[4:3] Address-Generation Sequence During Bursts
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 Burst Reads and Pipelined Burst Reads Figure 57 shows normal burst read cycles and a pipelined burst read cycle. The AMD-K6-2 processor drives CACHE# and ADS# together to specify that the current bus cycle is a burst cycle. If the processor samples KEN# asserted with the first BRDY#, it performs burst transfers. During the burst transfers, the system logic must ignore BE[7:0]# and must return all eight bytes beginning at the starting address the processor asserts on A[31:3]. Depending on the starting address, the system logic must determine the successive quadword addresses (A[4:3]) for each transfer in a burst, as shown in Table 27. The processor expects the second, third, and fourth quadwords to occur in the sequences shown in Table 27. Table 27. A[4:3] Address-Generation Sequence During Bursts Address Driven By Processor on A[4:3] Quadword 1 00b 01b 10b 11b Note: * quadword = 8 bytes A[4:3] Addresses of Subsequent Quadwords* Generated By System Logic Quadword 2 01b 00b 11b 10b Quadword 3 10b 11b 00b 01b Quadword 4 11b 10b 01b 00b In Figure 57, the processor drives CACHE# throughout all burst read cycles. In the first burst read cycle, the processor drives ADS# and CACHE#, then samples BRDY# on every clock edge starting with the clock edge after the clock edge that negates ADS#. The processor samples KEN# asserted on the clock edge on which the first BRDY# is sampled asserted, executes a 32-byte burst read cycle, and expects a total of four BRDY# signals. An ideal no-wait state access is shown in Figure 57, whereas most system logic solutions add wait states between the transfers. The second burst read cycle illustrates a similar sequence, but the processor samples NA# asserted on the same clock edge that the first BRDY# is sampled asserted. NA# assertion indicates the system logic is requesting the processor to output the next address early (also known as a pipeline transfer request). Without waiting for the current cycle to complete, the processor drives ADS# and related signals for the next burst cycle. Pipelining can reduce processor cycle-to-cycle idle times. 136 Bus Cycles Chapter 5