AMD AMD-K6-2/500AFX Data Sheet - Page 216
WBINVD and INVD, CacheLine Replacement, memory, after which the entire is invalidated. If a 1 is
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 WBINVD and INVD Cache-Line Replacement PF. If an attempt to invalidate or flush a page results in a page fault, the processor sets the PF bit to 1, and the invalidate or flush operation is not performed (even though invalidate operations do not normally generate page faults). In this case, an actual page fault exception is not generated. If the PF bit equals 0 after an invalidate or flush operation, then the operation executed successfully. The PF bit must be read after every write to the PFIR register to determine if the invalidate or flush operation executed successfully. F/I. This bit is used to control the type of action that occurs to the specified linear page. If a 0 is written to this bit, the operation is a flush, in which case all cache lines in the modified state within the specified page are written back to memory, after which the entire page is invalidated. If a 1 is written to this bit, the operation is an invalidation, in which case the entire page is invalidated without the occurrence of any writebacks. These x86 instructions cause all cache lines to be marked as invalid. WBINVD writes back modified lines before marking all cache lines invalid. INVD does not write back modified lines. Replacing lines in the instruction or data cache, according to the line replacement algorithms described in "Cache-Line Fills" on page 184, ensures coherency between main memory and the caches. Table 37 on page 197 shows all possible cache-line states before and after various cache-related operations. 196 Cache Organization Chapter 7