AMD AMD-K6-2/500AFX Data Sheet - Page 63
Paging, Kbyte Paging Mechanism
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21850J/0-February 2000 Preliminary Information AMD-K6®-2 Processor Data Sheet Paging The AMD-K6-2 processor can physically address up to four Gbytes of memory. This memory can be segmented into pages. The size of these pages is determined by the operating system design and the values set up in the page directory entries (PDE) and page table entries (PTE). The processor can access both 4-Kbyte pages and 4-Mbyte pages, and the page sizes can be intermixed within a page directory. When the page size extension (PSE) bit in CR4 is set, the processor translates linear addresses using either the 4-Kbyte translation lookaside buffer (TLB) or the 4-Mbyte TLB, depending on the state of the page size (PS) bit in the page directory entry. Figures 39 and 40 show how 4-Kbyte and 4-Mbyte page translations work. Page Page Directory Table 4-Kbyte Page Frame PTE PDE CR3 31 22 21 Page Directory Offset Figure 39. 4-Kbyte Paging Mechanism Page Table Offset 12 11 Linear Address Physical Address 0 Page Offset Chapter 3 Software Environment 43