Intel BX80605I7870 Data Sheet - Page 17
Device Mapping
UPC - 735858210461
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Register Description at DID of 2C22h. Device 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 0 and resides at DID of 2C23h. • Device 5: Integrated Memory Controller Channel 1. Device 5, Function 0 contains the control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C28h. Device 5, Function 1 contains the address registers for Integrated Memory Controller Channel 1 and resides at DID of 2C29h. Device 5, Function 2 contains the rank registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Ah. Device 5, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 1 and resides at DID of 2C2Bh. • Device 6: Integrated Memory Controller Channel 2. Device 6, Function 0 contains the control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C30h. Device 6, Function 1 contains the address registers for Integrated Memory Controller Channel 2 and resides at DID of 2C31h. Device 6, Function 2 contains the rank registers for Integrated Memory Controller Channel 2 and resides at DID of 2C32h. Device 6, Function 3 contains the thermal control registers for Integrated Memory Controller Channel 2 and resides at DID of 2C33h. 2.3 Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number, Device Number, and Function Number. Device configuration is based on the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. Table 2-1. Functions Specifically Handled by the Processor Component Register Group Intel QuickPath Architecture Generic Non-core Registers Intel QuickPath Architecture System Address Decoder Intel QPI Link 0 Intel QPI Physical 0 Integrated Memory Controller Registers Integrated Memory Controller Target Address Decoder Integrated Memory Controller RAS Registers Integrated Memory Controller Test Registers Integrated Memory Controller Channel 0 Control Processor Integrated Memory Controller Channel 0 Address Integrated Memory Controller Channel 0 Rank Integrated Memory Controller Channel 0 Thermal Control Integrated Memory Controller Channel 1 Control Integrated Memory Controller Channel 1 Address Integrated Memory Controller Channel 1 Rank Integrated Memory Controller Channel 1 Thermal Control Integrated Memory Controller Channel 2 Control Integrated Memory Controller Channel 2 Address Integrated Memory Controller Channel 2 Rank Integrated Memory Controller Channel 2 Thermal Control DID 2C41h 2C01h 2C10h 2C11 2C18h 2C19h 2C1Ah 2C1Ch 2C20h 2C21h 2C22h 2C23h 2C28h 2C29h 2C2Ah 2C2Bh 2C30h 2C31h 2C32h 2C33h Device Function 0 0 1 0 2 1 0 1 3 21 4 0 1 4 2 3 0 1 5 2 3 0 1 6 2 3 Notes: 1. Applies only to processors supporting sparing, mirroring, and scrubbing RAS features. Datasheet 17