Intel BX80605I7870 Data Sheet - Page 76
Mc_channel_0_scheduler_params
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Register Description 2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS MC_CHANNEL_1_SCHEDULER_PARAMS MC_CHANNEL_2_SCHEDULER_PARAMS These are the parameters used to control parameters within the scheduler. Device: 4, 5, 6 Function: 0 Offset: B8h Access as a Dword Bit 12 11 10:6 5 3 2:0 Type RW RW RW RW RW RW Reset Value Description CS_FOR_CKE_TRANSITION. 1 Specifies if chip select is to be asserted when CKE transitions with PowerDown entry/exit and SelfRefresh exit. FLOAT_EN. 0 When set, the address and command lines will float to save power when commands are not being sent out. This setting may not work with RDIMMs. PRECASRDTHRESHOLD. 7 Threshold above which Medium-Low Priority reads can PRE-CAS write requests. DISABLE_ISOC_RBC_RESERVE. 0 When set this bit will prevent any RBC's from being reserved for ISOC. 0 ENABLE2N. Enable 2n Timing. PRIORITYCOUNTER. 0 Upper 3 MSB of 8 bit priority time out counter. 2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS MC_CHANNEL_1_MAINTENANCE_OPS MC_CHANNEL_2_MAINTENANCE_OPS This register enables various maintenance operations such as Refreshes, ZQ, RCOMP, etc.. Device: 4, 5, 6 Function: 0 Offset: BCh Access as a Dword Bit 12:0 Type RW Reset Value Description MAINT_CNTR. 0 Value to be loaded in the maintenance counter. This counter sequences the rate to Refreshes, ZQ, RCOMP. 76 Datasheet
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