Intel BX80605I7870 Data Sheet - Page 63
Mc_channel_0_ddr3cmd, Mc_channel_1_ddr3cmd, Mc_channel_2_ddr3cmd
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Register Description 2.10.5 MC_CHANNEL_0_DDR3CMD MC_CHANNEL_1_DDR3CMD MC_CHANNEL_2_DDR3CMD DDR3 Configuration Command. This register is used to issue commands to the DIMMs such as MRS commands. The register is used by setting one of the *_VALID bits along with the appropriate address and destination RANK. The command is then issued directly to the DIMM. Care must be taken in using this register as there is no enforcement of timing parameters related to the action taken by a DDR3CMD write. This register has no effect after MC_CONTROL.INIT_DONE is set. Device: 4, 5, 6 Function: 0 Offset: 60h Access as a Dword Bit 28 27 26 25 24 23 22:20 19:16 15:0 Type RW RW RW RW RW RW RW RW RW Reset Value Description PRECHARGE_VALID. 0 Indicates current command is for a precharge command. ACTIVATE_VALID. 0 Indicates current command is for an activate command. REG_VALID. 0 Indicates current command is for a registered DIMM config write Bit is cleared by hardware on issuance. This bit applies only to processors supporting registered DIMMs. WR_VALID. 0 Indicates current command is for a write CAS. Bit is cleared by hardware on issuance. RD_VALID. 0 Indicates current command is for a read CAS. Bit is cleared by hardware on issuance. MRS_VALID. 0 Indicates current command is an MRS command. Bit is cleared by hardware on issuance. 0 RANK. Destination rank for command. MRS_BA. 0 Address bits driven to DDR_BA[2:0] pins for the DRAM command being issued due to a valid bit being set in this register. MRS_ADDR. 0 Address bits driven to DDR_MA pins for the DRAM command being issued due to a valid bit being set in this register. Datasheet 63