Intel BX80605I7870 Data Sheet - Page 69
Mc_channel_0_rank_timing_b, Mc_channel_1_rank_timing_b, Mc_channel_2_rank_timing_b
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Register Description 2.10.11 MC_CHANNEL_0_RANK_TIMING_B MC_CHANNEL_1_RANK_TIMING_B MC_CHANNEL_2_RANK_TIMING_B This register contains parameters that specify the rank timing used. All parameters are in DCLK. Device: 4, 5, 6 Function: 0 Offset: 84h Access as a Dword Bit 20:16 15:13 12:10 9 8:6 5:0 Type RW RW RW RW RW RW Reset Value Description B2B_CAS_DELAY. Controls the delay between CAS commands in DCLKS. The minimum spacing is 0 4 DCLKS. Values below 3 have no effect. A value of 0 disables the logic. Setting the value between 3-31 also spaces the read data by 0-29 DCLKS. The value entered is one less than the spacing required, i.e. a spacing of 5 DCLKS between CAS commands (or 1 DCLK on the read data) requires a setting of 4. tddWrTWr. Minimum delay between writes to different DIMMs. 000 = 2 001 = 3 010 = 4 0 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 tdrWrTWr. Minimum delay between writes to different ranks on the same DIMM. 000 = 2 001 = 3 010 = 4 0 011 = 5 100 = 6 101 = 7 110 = 8 111 = 9 tsrWrTWr. Minimum delay between writes to the same rank. 0 0 = 4 1 = 6 tRRD. 0 Specifies the minimum time between activate commands to the same rank. tFAW. 0 Four Activate Window. Specifies the time window in which four activates are allowed the same rank. Datasheet 69