Intel BX80605I7870 Data Sheet - Page 59
Integrated Memory Controller Channel Control, Registers
UPC - 735858210461
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Register Description Device: 3 Function: 1 Offset: C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh Access as a Dword Logical Channel2. Index 010 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode. 9:8 RW - 00 = Logical channel 0 01 = Logical channel 1 10 = Logical channel 2 11 = Reserved Logical Channel1. Index 001 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode. 5:4 RW - 00 = Logical channel 0 01 = Logical channel 1 10 = Logical channel 2 11 = Reserved Logical Channel0. Index 000 of the Interleave List. Bits determined from the matching TAD_DRAM_RULE mode. 1:0 RW - 00 = Logical channel 0 01 = Logical channel 1 10 = Logical channel 2 11 = Reserved 2.10 2.10.1 Integrated Memory Controller Channel Control Registers MC_CHANNEL_0_DIMM_RESET_CMD MC_CHANNEL_1_DIMM_RESET_CMD MC_CHANNEL_2_DIMM_RESET_CMD Integrated Memory Controller DIMM reset command register. This register is used to sequence the reset signals to the DIMMs. Device: 4, 5, 6 Function: 0 Offset: 50h Access as a Dword Bit Type Reset Value Description BLOCK_CKE. 2 RW 0 When set, CKE will be forced to be deasserted. ASSERT_RESET. 1 RW 0 When set, Reset will be driven to the DIMMs. RESET. 0 WO 0 Reset the DIMMs. Setting this bit will cause the Integrated Memory Controller DIMM Reset state machine to sequence through the reset sequence using the parameters in MC_DIMM_INIT_PARAMS. Datasheet 59