Intel BX80605I7870 Data Sheet - Page 84
Integrated Memory Controller Channel Address, Registers
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Register Description 2.11 2.11.1 Integrated Memory Controller Channel Address Registers MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2 Channel 0 DIMM Organization Descriptor Register. Device: 4 Function: 1 Offset: 48h, 4Ch, 50h Access as a Dword Bit Type 12:10 RW 9 RW 8:7 RW 6:5 RW 4:2 RW 1:0 RW Reset Value Description RANKOFFSET. Rank Offset for calculating RANK. This corresponds to the first logical rank on 0 the DIMM. The rank offset is always programmed to 0 for the DIMM 0 DOD registers. (DIMM 0 rank offset is always 0.) DIMM 1 DOD rank offset is either 4 for two DIMMs per channel or 2 if there are three DIMMs per channel. DIMM2 DOD rank offset is always 4 as it is only used in three DIMMs per channel case. 0 DIMMPRESENT. DIMM slot is populated. NUMBANK. Defines the number of (real, not shadow) banks on these DIMMs. 0 00 = Four-banked 01 = Eight-banked 10 = Sixteen-banked NUMRANK. Number of Ranks. Defines the number of ranks on these DIMMs. 0 00 = Single Ranked 01 = Double Ranked 10 = Quad Ranked NUMROW. Number of Rows. Defines the number of rows within these DIMMs. 000 = 2^12 Rows 0 001 = 2^13 Rows 010 = 2^14 Rows 011 = 2^15 Rows 100 = 2^16 Rows NUMCOL. Number of Columns. Defines the number of columns within on these DIMMs. 00 = 2^10 columns 0 01 = 2^11 columns 10 = 2^12 columns 11 = RSVD. 84 Datasheet
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