Intel BX80605I7870 Data Sheet - Page 62
Mc_channel_0_dimm_init_status, Mc_channel_1_dimm_init_status, Mc_channel_2_dimm_init_status
UPC - 735858210461
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Register Description 2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUS MC_CHANNEL_1_DIMM_INIT_STATUS MC_CHANNEL_2_DIMM_INIT_STATUS The initialization state is stored in this register. This register is cleared on a new training command. Device: 4, 5, 6 Function: 0 Offset: 5Ch Access as a Dword Bit Type Reset Value Description 9 RO 8 RO 7 RO 6 RO 5 RO 4 RO 3 RO 2:0 RO RCOMP_CMPLT. 0 When set, indicates that RCOMP command has complete. This bit is cleared by hardware on command issuance and set once the command is complete. INIT_CMPLT. 0 This bit is cleared when a new training command is issued. It is set once the sequence is complete regardless of whether all steps passed or not. ZQCL_CMPLT. 0 When set, indicates that ZQCL command has completed. This bit is cleared by hardware on command issuance and set once the command is complete. WR_DQ_DQS_PASS. 0 Set after a training command when the Write DQ-DQS training step passes. The bit is cleared by hardware when a new training command is sent. WR_LEVEL_PASS. 0 Set after a training command when the write leveling training step passes. The bit is cleared by hardware when a new training command is sent. RD_RCVEN_PASS. 0 Set after a training command when the Read Receive Enable training step passes. The bit is cleared by hardware when a new training command is sent. RD_DQ_DQS_PASS. 0 Set after a training command when the Read DQ-DQS training step passes. The bit is cleared by hardware when a new training command is sent. PHYFSMSTATE. The current state of the top level training FSM. 000 = IDLE 0 001 = RD DQ-DQS 010 = RcvEn Bitlock 011 = Write Level 100 = WR DQ-DQS 62 Datasheet