Intel BX80605I7870 Data Sheet - Page 88
Integrated Memory Controller Channel Rank, Registers
UPC - 735858210461
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Register Description 2.12 2.12.1 Integrated Memory Controller Channel Rank Registers MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1 MC_RIR_LIMIT_CH0_2, MC_RIR_LIMIT_CH0_3 MC_RIR_LIMIT_CH0_4, MC_RIR_LIMIT_CH0_5 MC_RIR_LIMIT_CH0_6, MC_RIR_LIMIT_CH0_7 MC_RIR_LIMIT_CH1_0, MC_RIR_LIMIT_CH1_1 MC_RIR_LIMIT_CH1_2, MC_RIR_LIMIT_CH1_3 MC_RIR_LIMIT_CH1_4, MC_RIR_LIMIT_CH1_5 MC_RIR_LIMIT_CH1_6, MC_RIR_LIMIT_CH1_7 MC_RIR_LIMIT_CH2_0, MC_RIR_LIMIT_CH2_1 MC_RIR_LIMIT_CH2_2, MC_RIR_LIMIT_CH2_3 MC_RIR_LIMIT_CH2_4, MC_RIR_LIMIT_CH2_5 MC_RIR_LIMIT_CH2_6, MC_RIR_LIMIT_CH2_7 Channel Rank Limit Range Registers. Device: 4 Function: 2 Offset: 40h, 44h, 48h, 4Ch, 50h, 54h, 58h, 5Ch Access as a Dword Bit Type Reset Value Description 9:0 RW LIMIT. This field specifies the top of the range being mapped to the ranks specified in 0 the MC_RIR_WAY_CH registers. The most significant bits of the lowest address in this range is one greater than the limit field in the RIR register with the next lower index. This field is compared against MA[37:28]. 88 Datasheet