Intel BX80605I7870 Data Sheet - Page 71
Mc_channel_0_cke_timing, Mc_channel_1_cke_timing, Mc_channel_2_cke_timing, 10.15,
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Register Description 2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMING MC_CHANNEL_2_CKE_TIMING This register contains parameters that specify the CKE timings. All units are in DCLK. Device: 4, 5, 6 Function: 0 Offset: 90h Access as a Dword Bit 31:24 23:21 20:11 10:3 2:0 Type RW RW RW RW RW Reset Value Description tRANKIDLE. Rank will go into powerdown after it has been idle for the specified number of 0 dclks. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN. If CKE is being shared between ranks then both ranks must be idle for this amount of time. A Power Down Entry command will be requested for a rank after this number of DCLKs if no request to the rank is in the MC. tXP. 0 Minimum delay from exit power down with DLL and any valid command. Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL. Slow exit precharge powerdown is not supported. tXSDLL. 0 Minimum delay between the exit of self refresh and commands that require a locked DLL. tXS. 0 Minimum delay between the exit of self refresh and commands not requiring a DLL. tCKE. 0 CKE minimum pulse width. 2.10.15 MC_CHANNEL_0_ZQ_TIMING MC_CHANNEL_1_ZQ_TIMING MC_CHANNEL_2_ZQ_TIMING This register contains parameters that specify ZQ timing. All units are DCLK unless otherwise specified. The register encodings are specified where applicable. Device: 4, 5, 6 Function: 0 Offset: 94h Access as a Dword Bit 30 29 28:8 7:5 4:0 Type RW RW RW RW RW Reset Value Description 1 1 16410 4 0 Parallel_ZQ. Enable ZQ calibration to different ranks in parallel. tZQenable. Enable the issuing of periodic ZQCS calibration commands. ZQ_Interval. Nominal interval between periodic ZQ calibration in increments of tREFI. tZQCS. This field specifies ZQCS cycles in increments of 16. This is the minimum delay between ZQCS and any other command. This register should be programmed to at least 64/16=4='100' to conform to the DDR3 specification. tZQInit. This field specifies ZQInit cycles in increments of 32. This is the minimum delay between ZQCL and any other command. This register should be programmed to at least 512/32=16='10000' to conform to the DDR3 specification. Datasheet 71
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