Intel BX80605I7870 Data Sheet - Page 91
MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13
UPC - 735858210461
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Register Description 2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1 MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3 MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5 MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7 MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9 MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11 MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_13 MC_RIR_WAY_CH2_14, MC_RIR_WAY_CH2_15 MC_RIR_WAY_CH2_16, MC_RIR_WAY_CH2_17 MC_RIR_WAY_CH2_18, MC_RIR_WAY_CH2_19 MC_RIR_WAY_CH2_20, MC_RIR_WAY_CH2_21 MC_RIR_WAY_CH2_22, MC_RIR_WAY_CH2_23 MC_RIR_WAY_CH2_24, MC_RIR_WAY_CH2_25 MC_RIR_WAY_CH2_26, MC_RIR_WAY_CH2_27 MC_RIR_WAY_CH2_28, MC_RIR_WAY_CH2_29 MC_RIR_WAY_CH2_30, MC_RIR_WAY_CH2_31 Channel Rank Interleave Way Range Registers. These registers allow the user to define the ranks and offsets that apply to the ranges defined by the LIMIT in the MC_RIR_LIMIT_CH registers. The mappings are as follows: RIR_LIMIT_CH{chan}[0] -> RIR_WAY_CH{chan}[3:0] RIR_LIMIT_CH{chan}[1] -> RIR_WAY_CH{chan}[7:6] RIR_LIMIT_CH{chan}[2] -> RIR_WAY_CH{chan}[11:10] RIR_LIMIT_CH{chan}[3] -> RIR_WAY_CH{chan}[15:14] RIR_LIMIT_CH{chan}[4] -> RIR_WAY_CH{chan}[19:18] RIR_LIMIT_CH{chan}[5] -> RIR_WAY_CH{chan}[23:22] RIR_LIMIT_CH{chan}[6] -> RIR_WAY_CH{chan}[27:26] RIR_LIMIT_CH{chan}[7] -> RIR_WAY_CH{chan}[31:28] Device: 6 Function: 2 Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh, B0h, B4h, B8h, BCh, C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh, E0h, E4h, E8h, ECh, F0h, F4h, F8h, FCh Access as a Dword Bit 13:4 3:0 Type RW RW Reset Value Description OFFSET. 0 This field defines the offset used in the rank interleave. This is a 2's complement value. RANK. This field defines which rank participates in WAY(n). If MC.CLOSEDPAGE=1, this field defines the DRAM rank selected when MemoryAddress[7:6]=(n). If 0 MC.CLOSEDPAGE=0, this field defines which rank is selected when MemoryAddress[13:12]=(n). (n) is the instantiation of the register. This field is organized by physical rank. Bits [3:2] are the encoded DIMM ID(slot). Bits [1:0] are the rank within that DIMM. Datasheet 91