Intel BX80605I7870 Data Sheet - Page 95
Mc_closed_loop0, Mc_closed_loop1, Mc_closed_loop2, Mc_throttle_offset0, Mc_throttle_offset1,
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Register Description 2.13.7 2.13.8 MC_CLOSED_LOOP0 MC_CLOSED_LOOP1 MC_CLOSED_LOOP2 This register controls the closed loop thermal response of the DRAM thermal throttle logic. It supports immediate thermal throttle and 2X refresh. In addition, the register is used to configure the throttling duty cycle. Device: 4, 5, 6 Function: 3 Offset: 84h Access as a Dword Bit 17:8 4 3:0 Type RW RW RW Reset Value Description MIN_THROTTLE_DUTY_CYC. 64 This parameter represents the minimum number of DCLKs of operation allowed after throttling. In order to provide actual command opportunities, the number of clocks between CKE de-assertion and first command should be considered. REF_2X_NOW. 0 Direct control of dynamic 2X refresh if MC_THERMAL_CONTROL.THROTTLE_MODE = 2. THROTTLE_NOW. 0 Throttler Vector to directly control throttling if MC_THERMAL_CONTROL.THROTTLE_MODE = 2. MC_THROTTLE_OFFSET0 MC_THROTTLE_OFFSET1 MC_THROTTLE_OFFSET2 Compared against bits [36:29] of virtual temperature of each rank stored in RANK_VIRTUAL_TEMP to determine the throttle point. Recommended value for each rank is 255. When there are more than 4 ranks attached to the channel, the thermal throttle logic is shared. Device: 4, 5, 6 Function: 3 Offset: 88h Access as a Dword Bit 31:24 23:16 15:8 7:0 Type RW RW RW RW Reset Value Description 0 RANK3. Rank 3 throttle offset. 0 RANK2. Rank 2 throttle offset. 0 RANK1. Rank 1 throttle offset. 0 RANK0. Rank 0 throttle offset. Datasheet 95