Intel BX80605I7870 Data Sheet - Page 81
Mc_channel_0_addr_match, Mc_channel_1_addr_match, Mc_channel_2_addr_match
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Register Description 2.10.36 MC_CHANNEL_0_ADDR_MATCH MC_CHANNEL_1_ADDR_MATCH MC_CHANNEL_2_ADDR_MATCH This register specifies the intended address or address range where ECC errors will be injected. It can be set to match memory address on a per channel basis. The address fields can be masked in the Mask bits. Any mask bits set to 1 will always match. To match all addresses, all of the mask bits can be set to 1. The MC_CHANNEL_X_ECC_ERROR_INJECT register can be used to set the trigger for the error injection. Device: 4, 5, 6 Function: 0 Offset: F0h Access as a Qword Bit 41 40 39 38 37 36 35:34 33:30 29:14 13:0 Type RW RW RW RW RW RW RW RW RW RW Reset Value Description 0 MASK_DIMM. 1 = If set, ignore DIMM address during address comparison. 0 MASK_RANK. 1 = If set, ignore RANK address during address comparison. 0 MASK_BANK. 1 = If set, ignore BANK address during address comparison. MASK_PAGE. 0 If set, ignore PAGE address during address comparison. 0 MASK_COL. 1 = If set ignore, COLUMN address during address comparison. DIMM. 0 DIMM address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM address and bit 34 represent the RANK address. RANK. 0 Rank address for 1 or 2DPC. For 3DPC, bits 36 and 35 represent the DIMM address and bit 34 represent the RANK address. 0 BANK. Bank address. 0 PAGE. Page address. 0 COLUMN. Column address. Datasheet 81