Intel BX80605I7870 Data Sheet - Page 73
Mc_channel_0_odt_params2, Mc_channel_1_odt_params2, Mc_channel_2_odt_params2, 10.19
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Register Description 2.10.18 MC_CHANNEL_0_ODT_PARAMS2 MC_CHANNEL_1_ODT_PARAMS2 MC_CHANNEL_2_ODT_PARAMS2 This register contains parameters that specify Forcing ODT on Specific ranks. This register is used in debug only and not during normal operation. Device: 4, 5, 6 Function: 0 Offset: A0h Access as a Dword Bit Type Reset Value Description 9 RW 0 MCODT_Writes. Drive MC ODT on reads and writes. 8 RW 0 FORCE_MCODT. Force MC ODT to always be asserted. 7 RW 0 FORCE_ODT7. Force ODT for Rank7 to always be asserted. 6 RW 0 FORCE_ODT6. Force ODT for Rank6 to always be asserted. 5 RW 0 FORCE_ODT5. Force ODT for Rank5 to always be asserted. 4 RW 0 FORCE_ODT4. Force ODT for Rank4 to always be asserted. 3 RW 0 FORCE_ODT3. Force ODT for Rank3 to always be asserted. 2 RW 0 FORCE_ODT2. Force ODT for Rank2 to always be asserted. 1 RW 0 FORCE_ODT1. Force ODT for Rank1 to always be asserted. 0 RW 0 FORCE_ODT0. Force ODT for Rank0 to always be asserted. 2.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RD MC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD This register contains the ODT activation matrix for RANKS 0 to 3 for Reads. Device: 4, 5, 6 Function: 0 Offset: A4h Access as a Dword Bit 31:24 23:16 15:8 7:0 Type RW RW RW RW Reset Value Description 1 ODT_RD3. Bit patterns driven out onto ODT pins when Rank3 is read. 1 ODT_RD2. Bit patterns driven out onto ODT pins when Rank2 is read. 4 ODT_RD1. Bit patterns driven out onto ODT pins when Rank1 is read. 4 ODT_RD0. Bit patterns driven out onto ODT pins when Rank0 is read. Datasheet 73
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