Intel BX80605I7870 Data Sheet - Page 50
Mc_smi_spare_dimm_error_status
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UPC - 735858210461
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Register Description 2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS SMI sparing DIMM error threshold overflow status register. This bit is set when the perDIMM error counter exceeds the specified threshold. The bit is reset by BIOS. Device: 3 Function: 0 Offset: 50h Access as a Dword Bit 13:12 11:0 Type RW0C RW0C Reset Value Description 0 REDUNDANCY_LOSS_FAILING_DIMM The ID for the failing DIMM when redundancy is lost. 0 DIMM_ERROR_OVERFLOW_STATUS This 12-bit field is the per dimm error overflow status bits. The organization is as follows: If there are three or more DIMMS on the channel: Bit 0 = DIMM 0 Channel 0 Bit 1 = DIMM 1 Channel 0 Bit 2 = DIMM 2 Channel 0 Bit 3 = DIMM 3 Channel 0 Bit 4 = DIMM 0 Channel 1 Bit 5 = DIMM 1 Channel 1 Bit 6 = DIMM 2 Channel 1 Bit 7 = DIMM 3 Channel 1 Bit 8 = DIMM 0 Channel 2 Bit 9 = DIMM 1 Channel 2 Bit 10 = DIMM 2 Channel 2 Bit 11 = DIMM 3 Channel 2 If there are one or two DIMMS on the channel: Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0 Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0 Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0 Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0 Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1 Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1 Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1 Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1 Bit 8 = DIMM 0, Ranks 0 and 1, Channel 2 Bit 9 = DIMM 0, Ranks 2 and 3, Channel 2 Bit 10 = DIMM 1, Ranks 0 and 1, Channel 2 Bit 11 = DIMM 1, Ranks 2 and 3, Channel 2 50 Datasheet
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