Intel SE7501HG2 Product Guide - Page 12

Intel® E7501 Chipset The SE7501HG2 server includes the Intel E7501 chipset (MCH, ICH3-S, P64H2), which provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI). MCH The E7501 MCH North Bridge (MCH) integrates three main functions: • An integrated high performance main memory subsystem • An HI 2.0 bus interface that provides a high-performance data flow path to the P64H2 (I/O Bridge) • An HI 1.5 bus that provides an interface to the ICH3-S (South Bridge) Other features provided by the MCH include the following: • Full support of ECC on the memory bus • Full support of Intel® x4 Single Device Data Correction on the memory interface with x4 DIMMs • Twelve deep in-order queue • Full support of registered DDR266 ECC DIMMs2 • Support for 12 GB of DDR memory • Memory scrubbing P64H2 The primary role of the P64H2 is to provide an integrated I/O bridge to the 64-bit PCI-X segments. This subsystem supports two peer 64-bit PCI-X segments, each with two 64-bit/100MHz PCI-X slots. The Adaptec* AIC-7902 embedded controller is enabled via one of the PCI-X segments of the P64H2. ICH3-S The primary role of the ICH3-S is to provide the gateway to all PC-compatible I/O devices and features. The SE7501HG2 uses the following ICH3-S features: • 32-bit/33 MHz PCI bus interface • Low Pin Count (LPC) bus interface • IDE interface, with Ultra DMA 100 capability • Universal Serial Bus (USB) interface • PC-compatible timer/counter and DMA controllers • APIC and 8259 interrupt controller • Power management • General purpose I/O • System RTC 2 DDR200 compliant ECC DIMMs can be used only if 400 MHz processors are installed 12 Intel Server Board SE7501HG2 Product Guide