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HP Superdome SX2000 User Service Guide, Seventh Edition - HP Integrity Superdo - Page 32

Processors, Cell Memory System, Rules for Processor Mixing

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Processors There are several Itanium and PA-RISC processor families supported by the processors are already installed on the cell board. All processors require that a minimum firmware version be installed. For the processors supported, seeTable 1-2. Table 1-2 Supported Processors and Minimum Firmware Versions Processor Family Minimum Firmware Version Intel ® Itanium® single-core processors with 9 MB cache 4.3e (IPF SFW 004.080.000) Intel ® Itanium® dual-core processors with 18 MB cache 5.5d (IPF SFW 005.024.000) Intel ® Itanium® dual-core processors with 24 MB cache 5.5d (IPF SFW 005.024.000) PA-8900 dual-core processor with 64 MB cache PDC_FW 042.009.000 Intel ® Itanium ® dual-core 9100 series processors with 18 8.6d (IPF SFW 009.022.000) MB cache Intel ® Itanium ® dual-core 9100 series processors with 24 8.6d (IPF SFW 009.022.000) MB cache Core Frequency 1.6 GHz 1.6 GHz 1.6 GHz 1.1 GHz 1.6 GHz 1.6 GHz Rules for Processor Mixing • Processor families cannot be mixed on a cell board or within a partition • Processor frequencies cannot be mixed on a cell board or within a partition • Cache sizes cannot be mixed on a cell board or within a partition • Major processor steppings cannot be mixed on a cell board or within a partition • Full support for Itanium and PA-RISC processors within the same complex but in different partitions Cell Memory System Each cell in the sx2000 system has its own independent memory subsystem. This memory subsystem consists of four logical memory subsystems that achieve a combined bandwidth of 17 GB/s peak, 14-16 GB/s sustained. This cell is the first of the Superdome designs to support the use of DDR I/O DRAM. These DIMMs are to be based on the DDR-II protocol, and the cell design supports DIMM capacities of 1, 2, or 4 GB using monolithic DRAMs. Nonmonolithic, (stacked) DRAMS are not supported on the sx2000. The additional capacitive load and requirement for additional chip selects is not accommodated by the new chipset. All DIMMs used in the sx2000 are compatible with those used in other new CEC platforms. However other platforms can support DIMMs based on nonmonolithic DRAMs that are incompatible with the sx2000. Cell memory is illustrated in Figure 1-10. 32 Overview

Section	Page
User Service Guide	1
Table of Contents	3
About This Document	13
Intended Audience	13
Document Organization	13
Typographic Conventions	13
Related Information	14
Publishing History	14
HP contact information	15
Documentation feedback	15
1 Overview	17
Server History and Specifications	17
Server Components	18
Power Subsystem	19
AC Power	20
DC Power	20
Power Sequencing	21
Enabling 48 Volts	21
Cooling System	21
Utilities Subsystem	22
Platform Management	22
UGUY	23
CLU Functionality	23
PM3 Functionality	23
System Clocks	24
Management Processor	24
Compact Flash	25
HUCB	25
Backplane	26
Crossbar Chip	26
Switch Fabrics	27
Backplane Monitor and Control	27
I2C Bus Distribution	27
Clock Subsystem	27
System Clock Distribution	27
Hot-Swap Oscillator	28
sx2000 RCS Module	28
Cabinet ID	29
Cell ID	29
Backplane Power Requirements and Power Distribution	29
CPUs and Memories	30
Cell Controller	31
Processor Interface	31
Processors	32
Cell Memory System	32
Memory Controller	33
DIMM Architecture	33
Memory Interconnect	33
Mixing Different Sized DIMMs	34
Memory Interleaving	34
Memory Bank Attribute Table	34
Cell Map	35
Link Interleaving	35
Memory Error Protection	35
DRAM Erasure	36
PDC Functional Changes	36
Platform Dependent Hardware	36
Reset	37
Cell OL*	37
I/O Subsystem	37
PCI-X Backplane Functionality	38
SBA Chip CC-to-Ropes	38
Ropes-to-PCI LBA Chip	39
PCI Slots	40
Mixed PCI-X and PCI Express I/O Chassis	40
PCI Hot-Swap Support	41
System Management Station	41
User Accounts	42
New Server Cabling	42
m-Link Cable	42
e-Link Cable	42
Clock Cable	44
Firmware	44
Itanium Firmware for HP Integrity Superdome/sx2000	44
Itanium System Firmware Functions	46
PA-RISC Firmware for HP 9000/sx2000 Servers	46
PA-RISC System Firmware Functions	47
Server Configurations	47
Server Errors	48
2 System Specifications	49
Dimensions and Weights	49
Component Dimensions	49
Component Weights	49
Shipping Dimensions and Weights	50
Electrical Specifications	50
Grounding	51
Circuit Breaker	51
Power Options	51
System Power Requirements	52
Component Power Requirements	53
IOX Cabinet Power Requirements	53
IOX Cabinet Power Cords	53
Environmental Requirements	54
Temperature and Humidity Specifications	54
Power Dissipation	54
Acoustic Noise Specification	56
Airflow	56
3 Installing the System	59
Introduction	59
Communications Interference	59
Electrostatic Discharge	59
Public Telecommunications Network Connection	60
Unpacking and Inspecting the System	60
Verifying Site Preparation	60
Gathering LAN Information	60
Verifying Electrical Requirements	60
Checking the Inventory	60
Inspecting the Shipping Containers for Damage	61
Inspection Precautions	62
Claims Procedures	62
Unpacking and Inspecting Hardware Components	62
Tools Required	63
Unpacking the Cabinet	63
Unpacking the PDCA	71
Returning Equipment	71
Setting Up the System	72
Moving the System and Related Equipment to the Installation Site	72
Unpacking and Installing the Blower Housings and Blowers	72
Attaching the Side Skins and Blower Side Bezels	75
Attaching the Side Skins	75
Attaching the Blower Side Bezels	77
Attaching the Leveling Feet and Leveling the Cabinet	79
Installing the Front Door Bezels and the Front and Rear Blower Bezels	79
Installing the Front Door Bezels	79
Installing the Rear Blower Bezel	81
Installing the Front Blower Bezel	82
Wiring Check	83
Installing and Verifying the PDCA	84
Checking Voltage	88
Removing the EMI Panels	89
Connecting the Cables	91
Routing the I/O Cables	91
Installing the Support Management Station	93
Installing the SMS Support Shelf	93
Connecting the SMS to the Superdome	94
SMS Software and Superdome Firmware Downloading Procedure	94
Configuring the Event Information Tools	95
Turning On Housekeeping Power	96
Connecting the MP to the Customer LAN	98
Connecting the MP to the Network	98
Setting the Customer IP Address	99
Booting and Verifying the System	101
Connecting to the MP	101
Powering On the System 48 V Power Supply	104
Booting the HP Integrity Superdome/sx2000 to an EFI Shell	104
Booting an HP 9000 sx2000 Server to BCH	106
Verifying the System	106
Running JET Software	108
Running JUST	108
Power Cycling After Using JET	109
Offline Diagnostic Environment	109
Attaching the Rear Kick Plates	109
Performing a Visual Inspection and Completing the Installation	110
Conducting a Post-Installation Check	112
4 Booting and Shutting Down the Operating System	113
Operating Systems Supported on Cell-based HP Servers	113
System Boot Configuration Options	114
HP 9000 Boot Configuration Options	114
HP Integrity Boot Configuration Options	114
Booting and Shutting Down HP-UX	118
HP-UX Support for Cell Local Memory	118
Adding HP-UX to the Boot Options List	118
Booting HP-UX	119
Standard HP-UX Booting	120
Single-User Mode HP-UX Booting	123
LVM-Maintenance Mode HP-UX Booting	126
Shutting Down HP-UX	127
Booting and Shutting Down HP OpenVMS I64	128
HP OpenVMS I64 Support for Cell Local Memory	129
Adding HP OpenVMS to the Boot Options List	129
Booting HP OpenVMS	131
Shutting Down HP OpenVMS	132
Booting and Shutting Down Microsoft Windows	133
Microsoft Windows Support for Cell Local Memory	133
Adding Microsoft Windows to the Boot Options List	134
Booting Microsoft Windows	135
Shutting Down Microsoft Windows	137
Booting and Shutting Down Linux	138
Linux Support for Cell Local Memory	138
Adding Linux to the Boot Options List	139
Booting Red Hat Enterprise Linux	140
Booting SuSE Linux Enterprise Server	141
Shutting Down Linux	142
A sx2000 LEDs	145
B Management Processor Commands	149
BO Command	149
CA Command	149
CC Command	150
CP Command	151
DATE Command	152
DC Command	152
DF Command	153
DI Command	154
DL Command	155
EL Command	155
HE Command	156
ID Command	157
IO Command	158
IT Command	159
LC Command	159
LS Command	160
MA Command	160
ND Command	161
PD Command	161
PE Command	162
PS Command	163
RE Command	164
RL Command	165
RR Command	166
RS Command	166
SA Command	167
SO Command	167
SYSREV Command	168
TC Command	169
TE Command	169
VM Command	170
WHO Command	170
XD Command	171
C Powering the System On and Off	173
Shutting Down the System	173
Checking System Configuration	173
Shutting Down the Operating System	175
Preparing the Partitions for Shutdown	176
Powering Off the System	177
Turning On Housekeeping Power	178
Powering On the System Using the PE Command	180
D Templates	183
Templates	183
Equipment Footprint Templates	185
Computer Room Layout Plan	185

Match case Limit results 1 per page

Processors

There are several Itanium and PA-RISC processor families supported by the processors are

already installed on the cell board. All processors require that a minimum firmware version be

installed. For the processors supported, see

Table 1-2

Table 1-2 Supported Processors and Minimum Firmware Versions

Core Frequency

Minimum Firmware Version

Processor Family

1.6 GHz

4.3e (IPF SFW 004.080.000)

Intel

Itanium

single-core processors with 9 MB cache

1.6 GHz

5.5d (IPF SFW 005.024.000)

Intel

Itanium

dual-core processors with 18 MB cache

1.6 GHz

5.5d (IPF SFW 005.024.000)

Intel

Itanium

dual-core processors with 24 MB cache

1.1 GHz

PDC_FW 042.009.000

PA-8900 dual-core processor with 64 MB cache

1.6 GHz

8.6d (IPF SFW 009.022.000)

Intel

Itanium

dual-core 9100 series processors with 18

MB cache

1.6 GHz

8.6d (IPF SFW 009.022.000)

Intel

Itanium

dual-core 9100 series processors with 24

MB cache

Rules for Processor Mixing

•

Processor families cannot be mixed on a cell board or within a partition

•

Processor frequencies cannot be mixed on a cell board or within a partition

•

Cache sizes cannot be mixed on a cell board or within a partition

•

Major processor steppings cannot be mixed on a cell board or within a partition

•

Full support for Itanium and PA-RISC processors within the same complex but in different

partitions

Cell Memory System

Each cell in the sx2000 system has its own independent memory subsystem. This memory

subsystem consists of four logical memory subsystems that achieve a combined bandwidth of

17 GB/s peak, 14-16 GB/s sustained. This cell is the first of the Superdome designs to support the

use of DDR I/O DRAM. These DIMMs are to be based on the DDR-II protocol, and the cell design

supports DIMM capacities of 1, 2, or 4 GB using monolithic DRAMs. Nonmonolithic, (stacked)

DRAMS are not supported on the sx2000. The additional capacitive load and requirement for

additional chip selects is not accommodated by the new chipset. All DIMMs used in the sx2000

are compatible with those used in other new CEC platforms. However other platforms can

support DIMMs based on nonmonolithic DRAMs that are incompatible with the sx2000. Cell

memory is illustrated in

Figure 1-10

Overview