Intel S1200BTL Product Specification - Page 128

Design and Environmental Specifications, Intel®, Server Board S1200BT TPS, Revision 1.0, Intel order

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Design and Environmental Specifications Intel®Server Board S1200BT TPS Table 53. Turn On/Off Timing Item Tsb_on_delay Tac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay Tpson_pwok Tpwok_on Tpwok_off Tpwok_low Tsb_vout T5VSB_holdup Description Delay from AC being applied to 5 VSB being within regulation. Delay from AC being applied to all output voltages being within regulation. Duration for which all output voltages stay within regulation after loss of AC. Measured at 80% of maximum load. Delay from loss of AC to de-assertion of PWOK. Measured at 80% of maximum load. Delay from PSON# active to output voltages within regulation limits. Delay from PSON# deactive to PWOK being deasserted. Delay from output voltages within regulation limits to PWOK asserted at turn on. Delay from PWOK de-asserted to output voltages (3.3 V, 5 V, 12 V, -12 V) dropping out of regulation limits. Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal. Delay from 5 VSB being in regulation to O/Ps being in regulation at AC turn on. Duration for which the 5 VSB output voltage stays within regulation after loss of AC. Minimum N/A N/A 21 20 5 N/A 100 1 100 50 70 Maximum 1500 2500 N/A N/A 400 50 500 N/A N/A 1000 N/A Units Msec Msec Msec Msec Msec Msec Msec Msec Msec Msec Msec Figure 50. Turn On/Off Timing (Power Supply Signals) 116 Revision 1.0 Intel order number G13326-003

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Design and Environmental Specifications
Intel®
Server Board S1200BT TPS
Revision 1.0
Intel order number G13326-003
116
Table 53. Turn On/Off Timing
Item
Description
Minimum
Maximum
Units
T
sb
_on_delay
Delay from AC being applied to 5 VSB being
within regulation.
N/A
1500
Msec
T
ac
_on_delay
Delay from AC being applied to all output
voltages being within regulation.
N/A
2500
Msec
T
vout
_holdup
Duration for which all output voltages stay within
regulation after loss of AC. Measured at 80% of
maximum load.
21
N/A
Msec
T
pwok
_holdup
Delay from loss of AC to de-assertion of PWOK.
Measured at 80% of maximum load.
20
N/A
Msec
T
pson
_on_delay
Delay from PSON# active to output voltages
within regulation limits.
5
400
Msec
T
pson
_pwok
Delay from PSON# deactive to PWOK being de-
asserted.
N/A
50
Msec
T
pwok
_on
Delay from output voltages within regulation limits
to PWOK asserted at turn on.
100
500
Msec
T
pwok
_off
Delay from PWOK de-asserted to output voltages
(3.3 V, 5 V, 12 V, -12 V) dropping out of
regulation limits.
1
N/A
Msec
T
pwok
_low
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
100
N/A
Msec
T
sb
_vout
Delay from 5 VSB being in regulation to O/Ps
being in regulation at AC turn on.
50
1000
Msec
T
5VSB
_holdup
Duration for which the 5 VSB output voltage stays
within regulation after loss of AC.
70
N/A
Msec
Figure 50. Turn On/Off Timing (Power Supply Signals)