Intel S1200BTL Product Specification - Page 141

Intel®, Server Board S1200BT TPS, Appendix C: POST Code Diagnostic LED Decoder, Revision 1.0, Intel - led codes

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Intel®Server Board S1200BT TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, you can use the diagnostic LEDs to identify the last POST process executed. Later in POST, the BIOS displays POST Error Codes on the video monitor in the Error Manager display. Any POST Error Codes are automatically logged in the event log. The Diagnostic LEDs are a set of LEDs found on the back edge of the server board. The exact implementation may differ for some boards, but in general there are 8 Diagnostic LEDs which form a 2 hex digit (8 bit) code read left-to-right as facing the rear of the server. An LED which is ON represents a 1 bit value, and an LED which is OFF represents a 0 bit value. The LED bit values are read as Most Significant Bit to the left, Least Significant Bit to the right. In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Table 57. POST Progress Code LED Example Upper Nibble LEDs Lower Nibble LEDs MSB LEDs LED #7 LED #6 LED #5 LED #4 LED #3 LED #2 LED #1 8h 4h 2h 1h 8h 4h 2h Status ON OFF ON OFF ON OFF ON Results 1 0 1 0 1 1 0 Ah Ch  Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh. LSB LED #0 1h OFF 0 Progress Code 0x01 0x02 0x03 0x05 Table 58. POST Progress Codes Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB #7 #6 #5 #4 #3 #2 #1 #0 SEC Phase X X X X X X X O X X X X X X O X X X X X X X O O X X X X X O X O Description First POST code after CPU reset CPU Microcode load begin Cache As RAM initialization begin SEC Core at Power On Begin. Revision 1.0 129 Intel order number G13326-003

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Intel®
Server Board S1200BT TPS
Appendix C: POST Code Diagnostic LED Decoder
Revision 1.0
Intel order number G13326-003
129
Appendix C: POST Code Diagnostic LED Decoder
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, you can use the diagnostic LEDs to identify the last POST process executed.
Later in POST, the BIOS displays POST Error Codes on the video monitor in the Error Manager
display. Any POST Error Codes are automatically logged in the event log.
The Diagnostic LEDs are a set of LEDs found on the back edge of the server board. The exact
implementation may differ for some boards, but in general there are 8 Diagnostic LEDs which
form a 2 hex digit (8 bit) code read left-to-right as facing the rear of the server.
An LED which is ON represents a 1 bit value, and an LED which is OFF represents a 0 bit value.
The LED bit values are read as Most Significant Bit to the left, Least Significant Bit to the right.
In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The
LEDs are decoded as follows:
Table 57. POST Progress Code LED Example
LEDs
Upper Nibble LEDs
Lower Nibble LEDs
MSB
LSB
LED #7
LED #6
LED #5
LED #4
LED #3
LED #2
LED #1
LED #0
8h
4h
2h
1h
8h
4h
2h
1h
Status
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Results
1
0
1
0
1
1
0
0
Ah
Ch
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are
concatenated as ACh.
Table 58. POST Progress Codes
Progress Code
Diagnostic LED Decoder
O = On, X=Off
Upper Nibble
Lower Nibble
MSB 8h 4h 2h 1h
8h 4h 2h 1h LSB
#7 #6 #5 #4
#3 #2 #1 #0
Description
SEC Phase
0x01
X
X
X
X
X
X
X
O
First POST code after CPU reset
0x02
X
X
X
X
X
X
O
X
CPU Microcode load begin
0x03
X
X
X
X
X
X
O
O
Cache As RAM initialization begin
0x05
X
X
X
X
X
O
X
O
SEC Core at Power On Begin.