Intel S1200BTL Product Specification - Page 151

Intel®Server Board S1200BT TPS Glossary Term PECI PEF PEP PIA PLD PMI POST PSMI PWM QPI RAM RASUM RISC RMII ROM RTC SDR SECC SEEPROM SEL SIO SMBUS SMI SMM SMS SNMP SPS SSE2 SSE3 SSE4 TBD TDP TIM UART UDP UHCI URS UTC VID VRD VT Word WS-MAN Definition Platform Environment Control Interface Platform Event Filtering Platform Event Paging Platform Information Area (This feature configures the firmware for the platform hardware) Programmable Logic Device Platform Management Interrupt Power-On Self Test Power Supply Management Interface Pulse-Width Modulation QuickPath Interconnect Random Access Memory Reliability, Availability, Serviceability, Usability, and Manageability Reduced Instruction Set Computing Reduced Media-Independent Interface Read Only Memory Real-Time Clock (Component of ICH peripheral chip on the server board) Sensor Data Record Single Edge Connector Cartridge Serial Electrically Erasable Programmable Read-Only Memory System Event Log Server Input/Output System Management BUS Server Management Interrupt (SMI is the highest priority non-maskable interrupt) Server Management Mode Server Management Software Simple Network Management Protocol Server Platform Services Streaming SIMD Extensions 2 Streaming SIMD Extensions 3 Streaming SIMD Extensions 4 To Be Determined Thermal Design Power Thermal Interface Material Universal Asynchronous Receiver/Transmitter User Datagram Protocol Universal Host Controller Interface Unified Retention System Universal Time Coordinate Voltage Identification Voltage Regulator Down Virtualization Technology 16-bit quantity Web Services for Management Revision 1.0 139 Intel order number G13326-003