Intel S1200BTL Product Specification - Page 75

Screen Field Descriptions - ram

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Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Processor ID Option Values: Help Text: Comments: Information only. Displays the Processor Signature value (from the CPUID instruction) identifying the type of processor and the stepping Processor Frequency Option Values: Help Text: Comments: Information only. Displays current operating frequency of the processor. 2. Microcode Revision Option Values: Help Text: Comments: Information only. Displays Revision Level of the currently loaded processor microcode. 3. L1 Cache RAM Option Values: Help Text: Comments: Information only. Displays size in KB of the processor L1 Cache. Since L1 cache is not shared between cores, this is shown as the amount of L1 cache per core. There are two types of L1 cache for the SandyBridge processor family, this amount is the total of L1 Instruction Cache plus L1Data Cache for each core. 4. L2 Cache RAM Option Values: Help Text: Comments: Information only. Displays size in KB of the processor L2 Cache. Since L2 cache is not shared between cores, this is shown as the amount of L2 cache per core. 5. L3 Cache RAM Option Values: Help Text: Comments: Information only. Displays size in MB of the processor L3 Cache. Since L3 cache is shared between all cores in a processor package, this is shown as the total amount of L3 cache per processor package. S1200BT boards have a single processor display. Romley boards have ―N/A‖ for the second processor if not installed. 6. Processor Version Revision 1.0 63 Intel order number G13326-003

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Intel®
Server Board S1200BT TPS
BIOS User Interface
Revision 1.0
Intel order number G13326-003
63
Screen Field Descriptions:
1.
Processor ID
Option Values:
<CPUID>
Help Text:
<None>
Comments:
Information only. Displays the Processor Signature value (from the
CPUID instruction) identifying the type of processor and the stepping Processor
Frequency
Option Values:
<Current Processor Operating Frequency>
Help Text:
<None>
Comments:
Information only. Displays current operating frequency of the processor.
2.
Microcode Revision
Option Values:
<Microcode Revision Number>
Help Text:
<None>
Comments:
Information only. Displays Revision Level of the currently loaded
processor microcode.
3.
L1 Cache RAM
Option Values:
<L1 cache size>
Help Text:
<None>
Comments:
Information only. Displays size in KB of the processor L1 Cache. Since
L1 cache is not shared between cores, this is shown as the amount of L1 cache per
core. There are two types of L1 cache for the SandyBridge processor family, this
amount is the total of L1 Instruction Cache plus L1Data Cache for each core.
4.
L2 Cache RAM
Option Values:
<L2 cache size>
Help Text:
<None>
Comments:
Information only. Displays size in KB of the processor L2 Cache. Since
L2 cache is not shared between cores, this is shown as the amount of L2 cache per
core.
5.
L3 Cache RAM
Option Values:
<L3 cache size>
Help Text:
<None>
Comments:
Information only. Displays size in MB of the processor L3 Cache. Since
L3 cache is shared between all cores in a processor package, this is shown as the total
amount of L3 cache per processor package. S1200BT boards have a single processor
display. Romley boards have
―N/A‖ for the second processor if not installed.
6.
Processor Version