Intel S1200BTL Product Specification - Page 34
I/O Sub-system - drivers
View all Intel S1200BTL manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 34 highlights
Functional Architecture Intel®Server Board S1200BT TPS USB host interface SMBus Host interface Serial Peripheral interface LAN interface ACPI interface 3.4 I/O Sub-system Intel® C200 Series PCH provides extensive I/O support. 3.4.1 Digital Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C202 chipset. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. 3.4.2 PCI Express Interface The PCI-E configurations for each SKU are defined below: Intel® Server Board S1200BTL One PCI-E x16 connector to be used as a x8 link, two PCI-E x8 connectors to be used as a x4 link and one SAS module connector to be used as a x4 link connected to the PCI-E ports of the processor. One PCI-E x8 connector to be used as x4 link connected to the PCE ports of PCH. Intel® Server Board S1200BTS One PCI-E x16 connector to be used as x8 link, one PCI-E x8 connectors to be used as a x8 link connected to the PCI-E ports of the processor. One PCI-E x8 connector to be used as x4 link connected to the PCI-E ports of PCH. There is one 32-bit, 33-MHz 5-V PCI slot, common on both SKUs. Compatibility with the PCI addressing model is maintained to ensure all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-andPlay specification. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s each direction, which provides a 250-MB/s communications channel in each direction (500 MB/s total). This is close to twice the data rate of classic PCI. It is a fact that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would imply 300 MB/s. The external graphics ports support 5.0 GT/s speed as well. Operating at 5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s operation. When operating with two PCI Express* controllers, each controller can operate at either 2.5 GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. 3.4.3 Serial ATA Support The Intel® C200 Series chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6.0 Gb/s on up to two ports (Port 0 and 1 Only on S1200BTL) while all ports support rates up to 3.0 Gb/s. The SATA controller contains two modes of operation - a legacy mode using I/O space, 22 Revision 1.0 Intel order number G13326-003