Intel S1200BTL Product Specification - Page 145

Appendix D: POST Code Errors

Page 145 highlights

Intel®Server Board S1200BT TPS Appendix D: POST Code Errors Appendix D: POST Code Errors The BIOS outputs the current boot progress codes on the video screen. Progress codes are 32bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs. The Response section in the following table is divided into three types:  No Pause: The message displays on the screen during POST or in the Error Manager. The system continues booting with a degraded state. The user may want to replace the erroneous unit. The setup POST error Pause setting does not have any effect with this error.  Pause: The message displays on the Error Manager screen, and an error is logged to the SEL. The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error, where the user can take immediate corrective action or choose to continue booting.  Halt: The message displays on the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user must replace the faulty part and restart the system. The setup POST error Pause setting does not have any effect with this error. For example:  Error Code 8540 = DIMM_A1 disabled o Error Class 85 = DIMM error o Error Subclass 4 = DIMM disabled o Error Descriptor 0 = DIMM_A1 is the DIMM that has been disabled Be aware that these POST Error Codes must be coordinated with the Server Management Utilities team, which maintains a ―master list‖ of these codes. Table 59. POST Error Codes and Messages Error Code 0012 0048 0140 0141 0146 5220 5221 5224 8160 Error Message CMOS date/time not set Password check failed PCI component encountered a PERR error PCI resource conflict PCI out of resources error CMOS/NVRAM configuration cleared Passwords cleared by jumper Password clear jumper is Set Processor 01 unable to apply microcode update Response Major Major Major Major Major Major Major Major Major Revision 1.0 133 Intel order number G13326-003

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153

Intel®
Server Board S1200BT TPS
Appendix D: POST Code Errors
Revision 1.0
Intel order number G13326-003
133
Appendix D: POST Code Errors
The BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-
bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation
information. The class and subclass fields point to the type of hardware that is being initialized.
The operation field represents the specific initialization activity. Based on the data bit availability
to display progress codes, a progress code can be customized to fit the data width. The higher
the data bit, the higher the granularity of information that can be sent on the progress port. The
progress codes may be reported by the system BIOS or option ROMs.
The Response section in the following table is divided into three types:
No Pause:
The message displays on the screen during POST or in the Error Manager.
The system continues booting with a degraded state. The user may want to replace the
erroneous unit. The setup POST error Pause setting does not have any effect with this
error.
Pause:
The message displays on the Error Manager screen, and an error is logged to
the SEL. The setup POST error Pause setting determines whether the system pauses to
the Error Manager for this type of error, where the user can take immediate corrective
action or choose to continue booting.
Halt:
The message displays on the Error Manager screen, an error is logged to the
SEL, and the system cannot boot unless the error is resolved. The user must replace
the faulty part and restart the system. The setup POST error Pause setting does not
have any effect with this error.
For example:
Error Code
8540
=
DIMM_A1 disabled
o
Error Class 85
=
DIMM error
o
Error Subclass 4
=
DIMM disabled
o
Error Descriptor 0
=
DIMM_A1 is the DIMM that has been disabled
Be aware that these POST Error Codes must be coordinated with the Server Management
Utili
ties team, which maintains a ―master list‖ of these codes
.
Table 59. POST Error Codes and Messages
Error Code
Error Message
Response
0012
CMOS date/time not set
Major
0048
Password check failed
Major
0140
PCI component encountered a PERR error
Major
0141
PCI resource conflict
Major
0146
PCI out of resources error
Major
5220
CMOS/NVRAM configuration cleared
Major
5221
Passwords cleared by jumper
Major
5224
Password clear jumper is Set
Major
8160
Processor 01 unable to apply microcode update
Major