HP Dc7700 HP Compaq dx7300 and dc7700 Business PC Technical Reference Guide, 1 - Page 47

instructions dealing with branching sequences that are checked when re-occurring branches are - cpu support

Page 47 highlights

Processor/Memory Subsystem Figure 3-2 illustrates the basic internal architecture of an Intel Pentium single-core processor. Dual-core processors feature two cores operating in parallel. The table below provides a representative listing of supported processors. Other models may also be supported. Intel PPeenntituiummS4inPgrloecCesosreorProcessor Branch Prediction 16-K Execution Trace Cache CPU Rapid Exe. Eng. AALLUUss Out-of-Order Core 128-bit Integer FPU FSB I/F 8-K LL11 CDaacthae Cache L2 Adv.. Transfer Cache Core speed ALU Speed (Core speed x2) FSB speed (max. data transfer rate) Intel Model No. E6700 E6600 E6400 E6300 965 960 955 950 940 930 920 840 672 670 660 650 640 630 Dual Core? Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No Core Speed 2.66 GHz 2.40 GHz 2.13 GHz 1.86 GHz 3.73 GH 3.60 GHz 3.46 GHz 3.40 GHz 3.20 GHz 3.00 GHz 2.80 GHz 3.20 GHz 3.80 GHz 3.80 GHz 3.60 GHz 3.40 GHz 3.20 GHz 3.00 GHz FSB Speed 1066 MHz 1066 MHz 1066 MHz 1066 MHz 1066 MHz 800 MHz 1066 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz L2 Cache Size 4 MB 4 MB 2 MB 2 MB 2 x 2 MB 2 x 2 MB 2 x 2 MB 2 x 2 MB 2 x 2 MB 2 x 2 MB 2 x 2 MB 2 x 1 MB 2 MB 2 MB 2 MB 2 MB 2 MB 2 MB Hyper-Threading Technology? No No No No Yes No Yes No No No No No Yes Yes Yes Yes Yes Yes Figure 3-2. Supported Pentium and Core 2 Duo Processors (partial listing) The Intel Pentium processor increases processing speed by using higher clock speeds with hyper-pipelined technology, therefore handling significantly more instructions at a time. The Arithmetic Logic Units (ALUs) of all processors listed above run at twice the core speed. An improved branch prediction mechanism features an execution trace cache and a refined prediction algorithm. The execution trace cache can store 12 kilobytes of micro-ops (decoded instructions dealing with branching sequences) that are checked when re-occurring branches are processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the case in earlier generation Pentium processors. The Pentium processor is compatible with software written for x86 processors. These systems also support the Intel Celeron D processors and the energy-efficient Intel CoreT M 2 Duo processors. Technical Reference Guide www.hp.com 3-3

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
  • 147
  • 148
  • 149
  • 150
  • 151
  • 152
  • 153
  • 154
  • 155
  • 156
  • 157
  • 158
  • 159
  • 160
  • 161
  • 162
  • 163
  • 164
  • 165
  • 166
  • 167
  • 168
  • 169
  • 170
  • 171
  • 172
  • 173
  • 174
  • 175
  • 176
  • 177
  • 178
  • 179
  • 180
  • 181
  • 182
  • 183
  • 184
  • 185
  • 186
  • 187
  • 188
  • 189
  • 190
  • 191
  • 192
  • 193
  • 194
  • 195
  • 196

Technical Reference Guide
www.hp.com
3-3
Processor/Memory Subsystem
Figure 3-2 illustrates the basic internal architecture of an Intel Pentium single-core processor.
Dual-core processors feature two cores operating in parallel. The table below provides a
representative listing of supported processors. Other models may also be supported.
Figure 3-2. Supported Pentium and Core 2 Duo Processors (partial listing)
The Intel Pentium processor increases processing speed by using higher clock speeds with
hyper-pipelined technology, therefore handling significantly more instructions at a time. The
Arithmetic Logic Units (ALUs) of all processors listed above run at twice the core speed.
An improved branch prediction mechanism features an execution trace cache and a refined
prediction algorithm. The execution trace cache can store 12 kilobytes of micro-ops (decoded
instructions dealing with branching sequences) that are checked when re-occurring branches are
processed. Code that is not executed (bypassed) is no longer stored in the L1 cache as was the
case in earlier generation Pentium processors.
The Pentium processor is compatible with software written for x86 processors. These systems
also support the Intel Celeron D processors and the energy-efficient Intel Core
TM
2 Duo
processors.
Intel Model
No.
Dual
Core?
Core
Speed
FSB
Speed
L2 Cache
Size
Hyper-Threading
Technology?
E6700
Yes
2.66 GHz
1066 MHz
4 MB
No
E6600
Yes
2.40 GHz
1066 MHz
4 MB
No
E6400
Yes
2.13 GHz
1066 MHz
2 MB
No
E6300
Yes
1.86 GHz
1066 MHz
2 MB
No
965
Yes
3.73 GH
1066 MHz
2 x 2 MB
Yes
960
Yes
3.60 GHz
800 MHz
2 x 2 MB
No
955
Yes
3.46 GHz
1066 MHz
2 x 2 MB
Yes
950
Yes
3.40 GHz
800 MHz
2 x 2 MB
No
940
Yes
3.20 GHz
800 MHz
2 x 2 MB
No
930
Yes
3.00 GHz
800 MHz
2 x 2 MB
No
920
Yes
2.80 GHz
800 MHz
2 x 2 MB
No
840
Yes
3.20 GHz
800 MHz
2 x 1 MB
No
672
No
3.80 GHz
800 MHz
2 MB
Yes
670
No
3.80 GHz
800 MHz
2 MB
Yes
660
No
3.60 GHz
800 MHz
2 MB
Yes
650
No
3.40 GHz
800 MHz
2 MB
Yes
640
No
3.20 GHz
800 MHz
2 MB
Yes
630
No
3.00 GHz
800 MHz
2 MB
Yes
128-bit
Integer
FPU
L2
Adv..
Transfer
Cache
FSB
I/F
Rapid Exe. Eng.
Branch
Prediction
CPU
16-K Execution
Trace Cache
Out-of-Order
Core
Core speed
FSB speed (max. data transfer rate)
L1
Cache
Intel Pentium Single Core Processor
ALUs