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SATA Configuration Registers, SATA Bus Master Control Registers, Table 5-1., Device 31/Function 2 - virtualization

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Input/Output Interfaces SATA Configuration Registers The SATA controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the SATA controller function (PCI device #31, function #2) are listed in Table 5-1. Table 5-1. SATA PCI Configuration Registers (82801, Device 31/Function 2) PCI Conf. Addr. Register Reset Value PCI Conf. Addr. Register Reset Value 00-01h Vender ID 8086h 0F..1Fh Reserved 0's 02-03h Device ID 24D1h 10-17h Pri. Cmd, Cntrl. Addrs. 1 (both) 04-05h PCI Command 0000h 18-1Fh Sec. Cmd, Cntrl. Addrs. 1 (both) 06-07h PCI Status 02B0h 20-23h BMstr Base Address 1 08h Revision ID 00h 2C, 2Dh Subsystem Vender ID 0000h 09h Programming 8Ah 2E, 2Fh Subsystem ID 0000h 0Ah Sub-Class 01h 34h Capabilities pointer 80h 0Bh Base Class Code 01h 3Ch Interrupt Line 00h 0Dh Master Latency Timer 00h 3Dh Interrupt Pin 01h 0Eh Header Type 00h 40-57h Timing, Control All 0's SATA Bus Master Control Registers The SATA interface can perform PCI bus master operations using the registers listed in Table 5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table. As indicated, these registers are virtually a copy of those used by EIDE operations discussed in the EIDE section. I/O Addr. Offset 00h 02h 04h 08h 0Ah 0Ch Table 5-2. IDE Bus Master Control Registers Size (Bytes) Register 1 Bus Master IDE Command (Primary) 1 Bus Master IDE Status (Primary) 4 Bus Master IDE Descriptor Pointer (Primary) 1 Bus Master IDE Command (Secondary) 2 Bus Master IDE Status (Secondary) 4 Bus Master IDE Descriptor Pointer (Secondary Default Value 00h 00h 0000 0000h 00h 00h 0000 0000h 5-2 www.hp.com Technical Reference Guide

Section	Page
Title	1
Contents	3
Chap_1_Introduction_final_review.pdf	7
Introduction	7
1.1 About this Guide	7
1.1.1 Online Viewing	7
1.1.2 Hardcopy	7
1.2 Additional Information Sources	7
1.3 Model Numbering Convention	7
1.4 Serial Number	9
1.5 Notational Conventions	9
1.5.1 Values	9
1.5.2 Ranges	9
1.5.3 Register Notation and Usage	9
1.5.4 Bit Notation and Byte Values	9
1.6 Common Acronyms and Abbreviations	10
Chap_2_System_Overview_final.pdf	17
System Overview	17
2.1 Introduction	17
2.2 Features	18
2.3 Mechanical Design	20
2.3.1 Cabinet Layouts	21
2.3.2 Chassis Layouts	26
2.3.3 Board Layouts	30
2.4 System Architecture	33
2.4.1 Intel Processor Support	35
2.4.2 Chipset	36
2.4.3 Support Components	37
2.4.4 System Memory	37
2.4.5 Mass Storage	38
2.4.6 Serial and Parallel Interfaces	38
2.4.7 Universal Serial Bus Interface	38
2.4.8 Network Interface Controller	38
2.4.9 Graphics Subsystem	39
2.4.10 Audio Subsystem	39
2.5 Specifications	40
Chap_3_Processor_final_review.pdf	45
Processor/Memory Subsystem	45
3.1 Introduction	45
3.2 Intel Pentium Processors	46
3.2.1 Intel Processor Overview	46
3.2.2 Processor Upgrading	48
3.3 Memory Subsystem	48
Chap_4_System_Support_final_review.pdf	53
System Support	53
4.1 Introduction	53
4.2 PCI Bus Overview	53
4.2.1 PCI 2.3 Bus Operation	54
4.2.2 PCI Express Bus Operation	58
4.2.3 Option ROM Mapping	60
4.2.4 PCI Interrupts	60
4.2.5 PCI Power Management Support	60
4.2.6 PCI Connectors	61
4.3 System Resources	63
4.3.1 Interrupts	63
4.3.2 Direct Memory Access	68
4.4 Real-Time Clock and Configuration Memory	71
4.4.1 Clearing CMOS	71
4.4.2 Standard CMOS Locations	72
4.5 System Management	72
4.5.1 Security Functions	72
4.5.2 Power Management	74
4.5.3 System Status	75
4.5.4 Thermal Sensing and Cooling	75
4.6 Register Map and Miscellaneous Functions	76
4.6.1 System I/O Map	76
4.6.2 SCH5317 I/O Controller Functions	77
Chap_5_Input-Output_Interfaces_final_review.pdf	79
Input/Output Interfaces	79
5.1 Introduction	79
5.2 SATA Interfaces	79
5.2.1 SATA Programming	79
5.2.2 SATA Connector	81
5.2.3 RAID Functionality	81
5.3 Diskette Drive Interface	82
5.3.1 Diskette Drive Programming	82
5.3.2 Diskette Drive Connector	86
5.4 Serial Interface	87
5.4.1 Serial Connector	87
5.4.2 Serial Interface Programming	87
5.5 Parallel Interface	89
5.5.1 Standard Parallel Port Mode	89
5.5.2 Enhanced Parallel Port Mode	89
5.5.3 Extended Capabilities Port Mode	90
5.5.4 Parallel Interface Programming	90
5.5.5 Parallel Interface Connector	92
5.6 Keyboard/Pointing Device Interface	93
5.6.1 Keyboard Interface Operation	93
5.6.2 Pointing Device Interface Operation	95
5.6.3 Keyboard/Pointing Device Interface Programming	95
5.6.4 Keyboard/Pointing Device Interface Connector	99
5.7 Universal Serial Bus Interface	100
5.7.1 USB Data Formats	101
5.7.2 USB Programming	102
5.7.3 USB Connector	103
5.7.4 USB Cable Data	104
5.8 Audio Subsystem	105
5.8.1 HD Audio Controller	106
5.8.2 HD Audio Interface	106
5.8.3 HD Audio Codec	107
5.8.4 Audio Programming	108
5.8.5 Audio Specifications	110
5.9 Network Interface Controller	111
5.9.1 Wake-On-LAN Support	112
5.9.2 Alert Standard Format Support	112
5.9.3 Power Management Support	112
5.9.4 NIC Programming	113
5.9.5 NIC Connector	113
5.9.6 NIC Specifications	114
Chap_6_Integrated_Graphics_final_review.pdf	115
Integrated Graphics Subsystem	115
6.1 Introduction	115
6.2 Functional Description	116
6.3 Display Modes	118
6.4 Upgrading Graphics	119
6.5 VGA Monitor Connector	120
Chap_7_Power_and_Signal_final_review.pdf	121
Power and Signal Distribution	121
7.1 Introduction	121
7.2 Power Supply Assembly/Control	121
7.2.1 Power Supply Assembly	122
7.2.2 Power Control	124
7.2.3 Power Management	127
7.3 Power Distribution	128
7.4 Signal Distribution	131
Chap_8_BIOS_ROM_final_review.pdf	135
BIOS ROM	135
8.1 Introduction	135
8.2 ROM Flashing	136
8.2.1 Upgrading	136
8.2.2 Changeable Splash Screen	137
8.3 Boot Functions	137
8.3.1 Boot Device Order	137
8.3.2 Network Boot (F12) Support	138
8.3.3 Memory Detection and Configuration	138
8.3.4 Boot Error Codes	139
8.4 Setup Utility	140
8.5 Client Management Functions	149
8.5.1 System ID and ROM Type	150
8.5.2 Temperature Status	150
8.5.3 Drive Fault Prediction	150
8.6 SMBIOS	151
8.7 USB Legacy Support	151
App_A_Error_Messages__amp__Codes_final_review.pdf	153
A.1 Introduction	153
A.2 Beep/Power LED Codes	153
A.3 Power-On Self Test (POST) Messages	154
A.4 System Error Messages (1xx-xx)	157
A.5 Memory Error Messages (2xx-xx)	158
A.6 Keyboard Error Messages (30x-xx)	159
A.7 Printer Error Messages (4xx-xx)	160
A.8 Video (Graphics) Error Messages (5xx-xx)	160
A.9 Diskette Drive Error Messages (6xx-xx)	161
A.10 Serial Interface Error Messages (11xx-xx)	162
A.11 Modem Communications Error Messages (12xx-xx)	163
A.12 System Status Error Messages (16xx-xx)	164
A.13 Hard Drive Error Messages (17xx-xx)	165
A.14 Hard Drive Error Messages (19xx-xx)	167
A.15 Video (Graphics) Error Messages (24xx-xx)	168
A.16 Audio Error Messages (3206-xx)	168
A.17 DVD/CD-ROM Error Messages (33xx-xx)	169
A.18 Network Interface Error Messages (60xx-xx)	169
A.19 SCSI Interface Error Messages (65xx-xx, 66xx-xx, 67xx-xx)	170
A.20 Pointing Device Interface Error Messages (8601-xx)	171
App_B_ASCII_Character_Set_final_review.pdf	173
B.1 Introduction	173
App_C_Keyboard_final_review.pdf	177
C.1 Introduction	177
C.2 Keystroke Processing	177
C.2.1 PS/2-Type Keyboard Transmissions	179
C.2.2 USB-Type Keyboard Transmissions	180
C.2.3 Keyboard Layouts	180
C.2.4 Keys	183
C.2.5 Keyboard Commands	186
C.2.6 Scan Codes	187
C.3 Connectors	193

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Technical Reference Guide

Input/Output Interfaces

SATA Configuration Registers

The SATA controller is configured as a PCI device with bus mastering capability. The PCI

configuration registers for the SATA controller function (PCI device #31, function #2) are listed

in Table 5-1.

SATA Bus Master Control Registers

The SATA interface can perform PCI bus master operations using the registers listed in Table

5-2. These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI

configuration register 20h in the previous table. As indicated, these registers are virtually a copy

of those used by EIDE operations discussed in the EIDE section.

Table 5-1.

SATA PCI Configuration Registers (82801, Device 31/Function 2)

PCI Conf.

Addr.

Reset

Value

PCI Conf.

Addr.

Reset

Value

00-01h

Vender ID

8086h

0F..1Fh

Reserved

0’s

02-03h

Device ID

24D1h

10-17h

Pri. Cmd, Cntrl.

Addrs.

1 (both)

04-05h

PCI Command

0000h

18-1Fh

Sec. Cmd, Cntrl.

Addrs.

1 (both)

06-07h

PCI Status

02B0h

20-23h

BMstr Base Address

08h

Revision ID

00h

2C, 2Dh

Subsystem Vender ID

0000h

09h

Programming

8Ah

2E, 2Fh

Subsystem ID

0000h

0Ah

Sub-Class

01h

34h

Capabilities pointer

80h

0Bh

Base Class Code

01h

3Ch

Interrupt Line

00h

0Dh

Master Latency Timer

00h

3Dh

Interrupt Pin

01h

0Eh

Header Type

00h

40-57h

Timing, Control

All 0’s

Table 5-2.

IDE Bus Master Control Registers

I/O Addr.

Offset

Size

(Bytes)

Default Value

00h

Bus Master IDE Command (Primary)

00h

02h

Bus Master IDE Status (Primary)

00h

04h

Bus Master IDE Descriptor Pointer (Primary)

0000 0000h

08h

Bus Master IDE Command (Secondary)

00h

0Ah

Bus Master IDE Status (Secondary)

00h

0Ch

Bus Master IDE Descriptor Pointer (Secondary

0000 0000h