HP Dc7700 HP Compaq dx7300 and dc7700 Business PC Technical Reference Guide, 1 - Page 59
Link Layer, Physical Layer, Table 4-4., PCI Express Byte Transfer
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System Support Link Layer The link layer provides data integrity by adding a sequence information prefix and a CRC suffix to the packet created by the transaction layer. Flow-control methods ensure that a packet will only be transferred if the receiving device is ready to accomodate it. A corrupted packet will be automatically re-sent. Physical Layer The PCI Express bus uses a point-to-point, high-speed TX/RX serial lane topology. One or more full-duplex lanes transfer data serially, and the design allows for scalability depending on end-point capabilities. Each lane consists of two differential pairs of signal paths; one for transmit, one for receive (Figure 4-4). System Board TX Device A RX PCI Express Card Device B Figure 4-4. PCI Express Bus Lane Each byte is transferred using 8b/10b encoding. which embeds the clock signal with the data. Operating at a 2.5 Gigabit transfer rate, a single lane can provide a data flow of 200 MBps. The bandwidth is increased if additional lanes are available for use. During the initialization process, two PCI Express devices will negotiate for the number of lanes available and the speed the link can operate at. In a x1 (single lane) interface, all data bytes are transferred serially over the lane. In a multi-lane interface, data bytes are distributed across the lanes using a multiplex scheme as shown in Table 4-4: Table 4-4. PCI Express Byte Transfer Byte # x1 x4 x8 Transfer Transfer Transfer Lane # Lane # Lane # 0 0 0 0 1 0 1 1 2 0 2 2 3 0 3 3 4 0 0 4 5 0 1 5 6 0 2 6 7 0 3 7 Technical Reference Guide www.hp.com 4-7