Toshiba M200-ST2002 Maintenance Manual - Page 21
Accelerated Graphics Port Interface: adheres to AGP2.0, AGP
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Page 21 highlights
1.1 Features 1 Hardware Overview q PCI chipset This gate array incorporates the following elements and functions • Intel Odem+(855PM Bstep) (North Bridge) − Banias/Dothan Processor System Bus Support − DRAM Controller supporting DDR333/DDR266, 2GB max − Accelerated Graphics Port Interface: adheres to AGP2.0, AGP×4 mode − Hub Link Interface − 593-ball 37.5×37.5 mm FC-BGA package • Intel ICH4-M (South Bridge) − Hub Link Interface − PCI Rev2.2 Interface (6 PCI REQ/GNT Pairs) − BusMaster IDE Controller (Ultra ATA 100/66/33) − USB 1.1/2.0 Controller 6 Ports (EHCI: Enhanced Host Controller) − I/O APIC (ACPI 1.06) − SMBus2.0 Controller − FWH Interface (BIOS) − LPC Interface (EC/KBC, Super I/O) − IRQ Controller − Serial Interrupt Controller − Power Management Controller − Deeper Sleep (C4) Support − Suspend/Resume Control − AC'97 2.2 Interface − Internal RTC − Internal LAN Controller (WfM2.0) − 421-ball 31×31mm BGA Package q PC Card Controller Gate Array (YEBISU-SS) • PCI interface (PCI Revisio n2.2) • CardBus/PC Card controller (Yenta2 Version2.2) • SD memory card controller (SDHC Ver.1.2) • SD IO card controller (Ver.1.0) • SmartMedia controller (SMHC Ver.01/SMIL1.0) • SIO (UART) controller (MS Debug Port Specification Ver.1.0) • Docking station interface • Q switch control, reset control • External device interface Portege M200 Maintenance Manual (960-457) 1-7
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