D-Link DGS-3627G Product Manual - Page 355

Type Offset Port Time Range xStack® DGS-3600 Series Layer 3 Managed Gigabit Ethernet Switch Selected profile based on Ethernet (MAC Address), IP address, Packet Content Mask, or IPv6. Ethernet instructs the Switch to examine the layer 2 part of each packet header. IP instructs the Switch to examine the IP address in each frame's header. Packet Content Mask instructs the Switch to examine the packet header. IPv6 instructs the Switch to examine the IPv6 part of the packet header. This field will instruct the Switch to mask the packet header beginning with the offset value specified: value (0-15) - Enter a value in hex form to mask the packet from the beginning of the packet to the 15th byte. value (16-31) - Enter a value in hex form to mask the packet from byte 16 to byte 31. value (32-47) - Enter a value in hex form to mask the packet from byte 32 to byte 47. value (48-63) - Enter a value in hex form to mask the packet from byte 48 to byte 63. value (64-79) - Enter a value in hex form to mask the packet from byte 64 to byte 79. The CPU Access Rule may be configured on a per-port basis by entering the port number of the Switch. Click the check box and enter the name of the Time Range settings that has been previously configured in the Time Range Settings window. This will set specific times when this CPU access rule will be implemented on the Switch. To view the settings of a previously correctly configured rule, click in the Access Rule Table to view the following window: Figure 6- 39. CPU Interface Filtering Rule Display window (Packet Content) 339