Epson LQ 1050 Technical Manual - Page 191

LPD781, Sginal

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REV.-A Table A-6. 1.LPD781 0/781 1 Port Functions Pin Sginal Direction Descriptions 1-8 PAO-7 In/Out Port A: Eight-bit l/O with output latch. l/O possible by mode A (MA) register. Output HIGH. 9-16 17-24 25 26 27, 29 PBO-7 PCO-7 NMI INT 1 MODE 1,0 In/Out In/Out In In In/Out Port B: Eight-bit 1/0 with output latch. l/O possible by mode B (MB) register. Output HIGH. Port C: Eight-bit 1/0 with output latch. Port/Control mode can be set by mode control C (MCC) register. Output HIGH Non-maskable interrupt of the edge trigger (trailing edge). Maskable interrupt input of the edge trigger (leading edge). Also used as the AC input zero cross detecting terminal. 7811 :O=LOW and 1 =HIGH 7810 modes set in accordance with external memory (see Table A-2) 28 30, 31 32 33 34-41 42 43 44 45 46 47-54 55-62 63 64 RESET X2,X1 Vss AVSS ANO-7 VAref AVCC RD WR ALE PFO-7 PDO-7 VDD Vcc In - - - In In - out out out LOW reset Crytal connection for built-in clock pulse. When clock pulses are supplied externally, input must be to X 1. Supply voltage, Vss, OV Analong Vss Eight analog inputs of the A/D converter. AN7-4 can be used as the input terminals to the detect the leading edge and to set the test flag upon detection of the trailing edge. Reference voltage Analog Vcc Read strobe. LOW at the read machine cycle and at reset, HIGH at other times. Write strobe. LOW during the write machine cycle and at reset, HIGH at other times. Address latch enable. Latches the lower 8 address bits to access external memory. Port F 78: 1 1: Port bit-by-bit 1/0 possible by mode F register. In extension mode gradual address output assignment is possible in accordance with the size of external memory. See Table A-3. 78 10: By setting modes O and 1, assignment to the address bus (AB 15-8) can be made in accordance with the size of the external memory. The remaining terminals can be used as l/O ports. See Table A-4. Port D 781 1: Port bit-by-bit 1/0 possible. In extension mode, PD7-O act as the multiplexed address/data but (AD7-0). 78 10: Multiplexed address/data bus to access external memory. Supply voltage, VDD +5v Supply voltage, Vcc +5v NOTE: "Direction" refers to the direction of signal flow as viewed from the CPU. A-5

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REV.-A
Table A-6.
1.LPD781
0/781 1 Port Functions
Pin
Sginal
Direction
Descriptions
1-8
PAO-7
In/Out
Port A: Eight-bit l/O with output latch. l/O possible by mode A (MA)
register. Output HIGH.
9-16
PBO-7
In/Out
Port B: Eight-bit
1/0
with output latch. l/O possible by mode B (MB)
register. Output HIGH.
17-24
PCO-7
In/Out
Port C: Eight-bit
1/0
with output latch. Port/Control mode can be set
by mode control C
(MCC)
register. Output HIGH
25
NMI
In
Non-maskable
interrupt of the edge trigger (trailing edge).
26
INT
1
In
Maskable interrupt input of the edge trigger (leading edge). Also used
as the AC input zero cross detecting terminal.
27, 29
MODE 1,0
In/Out
7811 :O=LOW and 1
=HIGH
7810 modes set in accordance with external memory (see Table A-2)
28
RESET
In
LOW reset
30, 31
X2,X1
—
Crytal
connection for built-in clock pulse. When clock pulses are
supplied externally, input must be to X 1.
32
Vss
—
Supply voltage,
Vss,
OV
33
AVSS
—
Analong
Vss
34-41
ANO-7
In
Eight analog inputs of the A/D converter. AN7-4 can be used as the
input terminals to the detect the leading edge and to set the test flag
upon detection of the trailing edge.
42
VAref
In
Reference voltage
43
AV
CC
—
Analog Vcc
44
RD
out
Read strobe. LOW at the read machine cycle and at reset, HIGH at
other
times.
45
WR
out
Write strobe. LOW during the write machine cycle and at reset, HIGH
at other times.
46
ALE
out
Address latch enable. Latches the lower 8 address bits to access
external memory.
47-54
PFO-7
Port F
78: 1 1: Port bit-by-bit
1/0
possible by mode F register. In extension
mode gradual address output assignment is possible in accordance
with the size of external memory. See Table A-3.
78 10: By setting modes O and 1, assignment to the address bus (AB
15-8) can be made in accordance with the size of the external memory.
The remaining terminals can be used as l/O ports. See Table A-4.
55-62
PDO-7
Port D
781 1: Port bit-by-bit
1/0
possible. In extension mode,
PD7-O
act as the
multiplexed address/data but
(AD7-0).
78 10: Multiplexed address/data bus to access external memory.
63
V
DD
Supply voltage,
V
DD
+5v
64
Vcc
Supply voltage, Vcc
+5v
NOTE: “Direction” refers to the direction of signal flow as viewed from the CPU.
A-5