Epson LQ 1050 Technical Manual - Page 76

REV.-A, Table 2-5. Pin Function of GA E05A16GA cent'd, Pin No., Signal, NOTE: Direction on

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REV.-A Table 2-5. Pin Function of GA (E05A16GA) (cent'd) Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 5 2 53 54 I 56 57 58 59 55 I 63 64 Signal Name PC4 PC5 PC6 PC7 PBO PB 1 PB2 PB3 PB4 PB5 PB6 PB7 Vss PA3 PA4 PA5 PA6 PA7 AO I A2 Cs RD WR DBO I DB3 Vrm Direction OUT OUT OUT - OUT OUT OUT OUT OUT OUT OUT - - IN IN IN - IN Function PAPER OUT LED ON/OFF Control Signal READY LED ON\ OFF control signal ON LINE LED ON/OFF control signal Not used DRAFT LED ON/OFF control signal ROMAN LED ON/OFF control signal SANS SERIF LED ON/OFF control signal 10 CPI (PICA) LED ON/OFF control signal 12 CPI (ELITE) LED ON/OFF control signal PS (PROPORTIONAL) LED ON/OFF control signal CONDENSED LED ON/OFF control signal Not used Logic ground LINE FEED switch FORM FEED switch LOAD/EJECT switch Not used Address bit (AO - A2) IN IN IN lN\OUT Chip Select signal input Read strobe signal Write strobe signal Input/Output data bus (DO - D3) IN Power source NOTE: "Direction" on the signal flow is as viewed from the gate array. 2-32 ,,

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REV.-A
Table 2-5. Pin Function of GA (E05A16GA) (cent’d)
Pin No.
Signal
Name
Direction
Function
36
PC4
OUT
PAPER OUT LED ON/OFF Control Signal
37
PC5
OUT
READY LED ON\ OFF control signal
38
PC6
OUT
ON LINE LED ON/OFF control signal
39
PC7
—
Not used
40
PBO
OUT
DRAFT LED ON/OFF control signal
41
PB 1
OUT
ROMAN LED ON/OFF control signal
42
PB2
OUT
SANS SERIF LED ON/OFF control signal
43
PB3
OUT
10
CPI
(PICA) LED ON/OFF control signal
44
PB4
OUT
12
CPI
(ELITE) LED ON/OFF control signal
45
PB5
OUT
PS (PROPORTIONAL) LED ON/OFF control signal
46
PB6
OUT
CONDENSED LED ON/OFF control signal
47
PB7
—
Not used
48
Vss
—
Logic ground
49
PA3
IN
LINE FEED switch
50
PA4
IN
FORM FEED switch
51
PA5
IN
LOAD/EJECT switch
5
2
PA6
—
Not used
53
PA7
54
AO
IN
Address bit (AO - A2)
I
I
56
A2
57
Cs
IN
Chip Select signal input
58
RD
IN
Read strobe signal
59
WR
IN
Write strobe signal
55
DBO
lN\OUT
Input/Output data bus (DO - D3)
I
I
63
DB3
64
Vrm
IN
Power source
NOTE: “Direction” on the signal flow is as viewed from the gate array.
2-32
,,