3Com 3C63311 Reference Guide - Page 244

232 APPENDIX B: PATHBUILDER S330/S310 MODULE AND APPLICATION OVERVIEW The T1-DSX/E1 inputs can be either ESF, SF, or no-framing using B8ZS or AMI. In accordance with the ATM Forum's Circuit Emulation Service (CES) specifications, the received frame can be broken up into its DSO and ABCD signaling components using structured mode or tunneled through the ATM network using unstructured mode. Structured mode allows DSO mid span drop and insert or grooming. n In structured format, the data is framed on, then any single 64K channel or a group of timeslots can be selected, grouped and SAR'd to a single ATM connection. In the T1-DSX/E1 format, up to 24 channels, or a combination thereof, can be selected. The timing in structured mode should be loop or system. See "Structured DS1" later in this section for further information on structured service and when to use it. n In unstructured format, the data is treated as bits in / bits out and is converted into cells with a single VP/VC connection. You can select the timing-loop, system, SRTS or adaptive-in unstructured mode. With SRTS timing, the internal system clock on both ends must be traceable to a common source. See "Unstructured DS1" later in this section for details on unstructured service and when to use it. On the T1-DSX/E1 receive side, the data flow is as follows: n A line interface unit recovers the digital data. n The data flows through a framer to extract the serial data stream. n The data is fed to the AAL1 SAR device. n The SAR converts the data into ATM cells and tags the cells with the internal VP/VC number. n The cells are passed through a FIFO to the CTX module. On the T1-DSX/E1 transmit side, the data flow is as follows: n Cells received from the CTX module are buffered in a 32-cell FIFO to decouple the CTX cells from the SAR. The depth of the FIFO is determined by the CDVT cell delay variation tolerance (CDVT) parameter that you set. n The cells are fed in the SAR, and the SAR terminates the AAL1 pointer overhead and places the payload in memory. For unstructured data, the clock is recovered using the adaptive or the SRTS technique-or it can be loop-timed. If the SRTS technique is used, the system clocks on both ends must be synchronized. n The clock and data are sent out to a framer chip where the frame is added and the signal is converted into analog. An 8 KHz clock is extracted from one of the T1-DSX/E1 clocks and fed to the motherboard connector. This clock is used as one of the options to derive the system clock. The module also accepts an 8 Khz clock from the motherboard to provide the T1-DSX/E1 and serial timing. For the serial interface, the data is clocked as a serial bit stream and transferred to the SAR, where it is converted into a structured path AAL1 stream. On the receive from the ATM side, the cells are passed from the CTX to the SAR and the original data is recovered. A timing option allows end-to-end clock recovery. The data is then sent serially over the connector. A sensing option in the cable allows automatic detection of DCE and V.35/RS-449 options.