AMD AMD-K6-2/500AFX Data Sheet - Page 110
APCHK# (Address Parity Check
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 4.8 Summary Driven APCHK# (Address Parity Check) Output If the processor detects an address parity error during an inquire cycle, APCHK# is asserted for one clock. The processor does not take an internal exception as the result of detecting an address bus parity check, and system logic must respond appropriately to the assertion of this signal. The processor is designed so that APCHK # does not glitch, enabling the signal to be used as a clocking source for system logic. APCHK# is driven valid off the clock edge after the clock edge on which the processor samples EADS# asserted. It is negated off the next clock edge. APCHK# is always driven except in the Tri-State Test mode. 90 Signal Descriptions Chapter 4