AMD AMD-K6-2/500AFX Data Sheet - Page 288
Clock Switching Characteristics for 100MHz Bus Operation, Table 61. - 500 -
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AMD-K6®-2 Processor Data Sheet Preliminary Information 21850J/0-February 2000 16.2 Clock Switching Characteristics for 100-MHz Bus Operation Table 61. CLK Switching Characteristics for 100-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments Frequency 33.3 MHz 100 MHz In Normal Mode t1 CLK Period 10.0 ns 95 In Normal Mode t2 CLK High Time 3.0 ns 95 t3 CLK Low Time 3.0 ns 95 t4 CLK Fall Time 0.15 ns 1.5 ns 95 t5 CLK Rise Time 0.15 ns 1.5 ns 95 CLK Period Stability ± 250 ps Note Note: Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz. 16.3 Clock Switching Characteristics for 66-MHz Bus Operation Table 62. CLK Switching Characteristics for 66-MHz Bus Operation Symbol Parameter Description Preliminary Data Min Max Figure Comments Frequency 33.3 MHz 66.6 MHz In Normal Mode t1 CLK Period 15.0 ns 30.0 ns 95 In Normal Mode t2 CLK High Time 4.0 ns 95 t3 CLK Low Time 4.0 ns 95 t4 CLK Fall Time 0.15 ns 1.5 ns 95 t5 CLK Rise Time 0.15 ns 1.5 ns 95 CLK Period Stability ± 250 ps Note Note: Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz. 268 Signal Switching Characteristics Chapter 16
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